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Visitor
Visitor
11,536 Views
Registered: ‎05-25-2015

Synthesis taking too long ...

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Hello everybody,

 

I just finished to write a pretty complete design on ISE 14.7 targetting a Virtex7 device. The behavioural simulation (on Isim) takes a while but works perfectly.

 

Therefore, I tried to move to the next step adding a Time Constraint by double clicking on my top module -> User Constraints -> Create Timing Constraints in the ISE interface. This action triggered the synthesis and it's now more than 24 hours that ISE is trying to "Optimize" one of my module.

 

I don't mind about letting the program running for other 24 or 48 hours but I am suspecting that something is wrong with my design ... I know that it might be pretty eavy since I use many logic cores instances but I am afraid it doesn't justify the delay for the synthesis . I attach you my design in case someone sees something wrong with it.

 

Does anyone have an idea about how to solve my problem ?

 

I thank you in advance,

 

 

Best regards

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Guide
Guide
17,983 Views
Registered: ‎01-23-2009

(I also didn't look at your code)...

 

There are two fairly common reasons for synthesis taking too long (and 24 hours is way too long).

 

One has to do with RAM inference. If the code is attempting to describe a RAM using a large array, but the array cannot be mapped to block RAM or distributed RAM, then the tools will implement it with a huge number of flip-flops - often way more than the tool can accommodate. This will eventually fail, but only after chewing on it for many hours.

 

If you are inferring RAMs, you need to make sure that your code doesn't try and violate any of these requirements

  - block RAMs can only do synchronous reads

  - RAM contents (block or distributed) cannot be reset (they can be initialized in the bitstream but not reset afterwards)

  - RAMs can only be read and written a finite number of times in the same clock (generally either one or two)

 

Another common reason for synthesis taking too long is the unrolling of loops. FOR loops in RTL simulation, just mean iteration. But in synthesis, they mean the creating of multiple iterations of some gates. If the loops are big, you can end up with huge circuits, which, again, will cause synthesis too choke.

 

These are only two possible reasons - there may be many more, but these have been the ones I have heard of the most.

 

Avrum

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Explorer
Explorer
11,528 Views
Registered: ‎11-25-2014

I did not look at your code so I don't know if there are mutliple clocks, but if there are then make sure you add constraints to identify any false paths between clock domains. Or if there are multicycle paths within one clock domain, add constraints to identify those. Basically, make sure the tool is not cranking away trying to meet false timing paths.

 

If you have no false paths then you'll' need to run some reports and find out which paths are killing the timing and fix those.

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Visitor
Visitor
11,526 Views
Registered: ‎05-25-2015

Dear rjsefton,

 

I thank you for your reply.

 

I only use one clock which is an input of the top module (called 'transmitter') and then, I send this clock to all the other modules.

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Teacher
Teacher
11,519 Views
Registered: ‎07-09-2009

A fair size design there

 

Have you simulated any of the modules individualy ?

 

It might be possible to localise the problem area by dividing up the design.

 

Why you using ISE for a Virtex 7 ?

   I think for the Virtex range Vivado is recomended even though ISE covers them

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor
Visitor
11,518 Views
Registered: ‎05-25-2015

I ran the behavioral simulation on each block separately and also on the whole system and it works perfectly. Do you mean I should try to synthetise and run a post-synthesis simulation on each block individually ?

 

I would love to use Vivado but unfortunaltely it's not free ...

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Highlighted
Guide
Guide
17,984 Views
Registered: ‎01-23-2009

(I also didn't look at your code)...

 

There are two fairly common reasons for synthesis taking too long (and 24 hours is way too long).

 

One has to do with RAM inference. If the code is attempting to describe a RAM using a large array, but the array cannot be mapped to block RAM or distributed RAM, then the tools will implement it with a huge number of flip-flops - often way more than the tool can accommodate. This will eventually fail, but only after chewing on it for many hours.

 

If you are inferring RAMs, you need to make sure that your code doesn't try and violate any of these requirements

  - block RAMs can only do synchronous reads

  - RAM contents (block or distributed) cannot be reset (they can be initialized in the bitstream but not reset afterwards)

  - RAMs can only be read and written a finite number of times in the same clock (generally either one or two)

 

Another common reason for synthesis taking too long is the unrolling of loops. FOR loops in RTL simulation, just mean iteration. But in synthesis, they mean the creating of multiple iterations of some gates. If the loops are big, you can end up with huge circuits, which, again, will cause synthesis too choke.

 

These are only two possible reasons - there may be many more, but these have been the ones I have heard of the most.

 

Avrum

View solution in original post

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Visitor
Visitor
11,493 Views
Registered: ‎05-25-2015

Thank you very much for all your answers !

 

After removing some input/output by using serilaliation and configuring the IP cores to use DSP instead of fabric, I was finally able to synthethise my circuit after about 30 hours. But the synthesis time is not a problem for me.

 

I am not using any RAM but I indeed use a very large number of loops to generate my code. Unfortunately, my design has to have a pretty fair size and I am afraid that those loops are unevitables ..

 

 

Thank you again for your help

 

 

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Visitor
Visitor
8,438 Views
Registered: ‎11-11-2013

Hi guys,

I have the same problem with my code. Synthesis is taking more than 2 days.

 

The code should combine a input data with changing length to output data with constant length of 128 bits. 

I do use an array of 2x128 bits and also a pointer to the array.

It stops at:

Optimizing unit <compression_zeros_combine>...

 

Does someone have an idea about what's wrong?

 

Best regards

 

 

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Teacher
Teacher
8,419 Views
Registered: ‎03-31-2012

@ivanov_marko this thread is more than a year old and your issue seems to be different. Create a new thread with more information.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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