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Anonymous
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Synthesizing Error "Xst:899"

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During synthesizing I got the following 2 errors.

 

ERROR:Xst:899 - "ASCII.v" line 96: The logic for <feed> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
ERROR:Xst:899 - "ASCII.v" line 97: The logic for <state> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

 

My program code is (full length program code is attached within the message)

 

always @(negedge feedback or negedge clkT) begin
        if(state===0)begin
            feed=1;              <-------------------------------------------------- error line 95
            state=1;             <-------------------------------------------------- error line 96
        end
        else begin
            feed=0;
            state=0;
        end
end

 

Please help, Urgent...

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Teacher
Teacher
3,419 Views
Registered: ‎09-09-2010

Re: Synthesizing Error "Xst:899"

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> always @(negedge feedback or negedge clkT) begin

Only one clock per process for synthesis. Even in Verilog!

------------------------------------------
"If it don't work in simulation, it won't work on the board."

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Highlighted
Teacher
Teacher
3,420 Views
Registered: ‎09-09-2010

Re: Synthesizing Error "Xst:899"

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> always @(negedge feedback or negedge clkT) begin

Only one clock per process for synthesis. Even in Verilog!

------------------------------------------
"If it don't work in simulation, it won't work on the board."

View solution in original post

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Anonymous
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2,765 Views

Re: Synthesizing Error "Xst:899"

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Thanxx... done... :)
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