SystemclockP is a Single ended but iostandard is LVDS_25 which is differential

[vaddi_iitg]

[Drc 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port systemClockN is Single-Ended but has an IOStandard of LVDS_25 which can only support Differential

I am getting this error

I am using Znyq zc702 board. I am using system clock 200MHZ . It gives differential output. I am using the template which is present in Vivado 2014.2 for IBUFDS. IBUFGDS is not there i those templates. Please help me

[umamahe · Accepted solution]

The following AR http://www.xilinx.com/support/answers/57109.html helps for your case.

Also refer http://www.xilinx.com/support/answers/38656.html. Concepts give idea about usage of differential pair signals

[yenigal]

Hi

This is due to incorrect constraints on the clock source.

Compare your constraints with the master constraints file section of below doc and correct them

http://www.xilinx.com/support/documentation/boards_and_kits/zc702_zvik/ug850-zc702-eval-bd.pdf

[vaddi_iitg]

My constraints are correct i checked it

[aher]

Hi,

if you have used differential input clock,

are you also using IBUFDS/IBUFGDS to convert it to single ended?

thanks,

Shreyas

[anusheel]

Hi,

Use IBUFGDS instead of IBUFDS.

Refer below link for more details and template related to IBUFGDS:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/7series_hdl.pdf

Let us know if you come across any issue.

Thanks,
Anusheel
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