cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sophia_123
Participant
Participant
2,060 Views
Registered: ‎10-17-2016

TEMAC constraints of Zynq 7000

Hi,

I am using a Zynq 7000 TEMAC core in my project.

According to the example design of the core,I have got the required constrains in the context of the example design except main example design controls,that depend on a specific board.The board I am using is Zybo,So I add the example design controls to UCF.example:

NET "mac_speed<0>" LOC=G15 | IOSTANDARD=LVCMOS33; #IO_L19N_T3_VREF_35
NET "mac_speed<1>" LOC=P15 | IOSTANDARD=LVCMOS33; #IO_L24P_T3_34
NET "gen_tx_data" LOC=W13 | IOSTANDARD=LVCMOS33; #IO_L4N_T0_34
NET "chk_tx_data" LOC=T16 | IOSTANDARD=LVCMOS33; #IO_L9P_T1_DQS_34

 

The constraints provided by example design are for example:

INST "*trimac_core*STATGEN*ipic_rd_clear*" TNM="stats_ref_to_host";
INST "*trimac_core*STATGEN*response_toggle*" TNM="stats_ref_to_host";
INST "*trimac_core*STATGEN*rd_data_ref*" TNM="stats_ref_to_host";
TIMESPEC "TS_stats_ref_to_host" = FROM "stats_ref_to_host" TO "clock_generator_clkout1" 8000 ps DATAPATHONLY;

 

when I map this project,there are errors:

Error:Place:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS18, VREF = NR, VCCO = 1.80, TERM = NONE, DIR =
INPUT, DRIVE_STR = NR
gmii_crs
update_speed
glbl_rst
gmii_col
reset_error
pause_req_s
config_board
mii_tx_clk
ERROR:Place:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS18, VREF = NR, VCCO = 1.80, TERM = NONE, DIR =
OUTPUT, DRIVE_STR = 12
gmii_txd<7>
gmii_txd<6>
gmii_txd<5>
gmii_txd<4>
gmii_txd<3>
gmii_txd<2>
gmii_txd<1>
gmii_txd<0>
gmii_tx_clk
activity_flash
frame_error
frame_errorn
tx_statistics_s
rx_statistics_s
phy_resetn
serial_response
gmii_tx_er
gmii_tx_en
mdc
activity_flashn
ERROR:Place:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS18, VREF = NR, VCCO = 1.80, TERM = NONE, DIR =
BIDIR, DRIVE_STR = 12
mdio
ERROR:Place:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS18, VREF = NR, VCCO = 1.80, TERM = NONE, DIR =
INPUT, DRIVE_STR = NR
gmii_rxd<7>
gmii_rxd<6>
gmii_rxd<5>
gmii_rxd<4>
gmii_rxd<3>
gmii_rxd<2>
gmii_rxd<1>
gmii_rxd<0>
gmii_rx_er
gmii_rx_dv
ERROR:Place:866 - Not enough valid sites to place the following IOBs:
IO Standard: Name = LVCMOS18, VREF = NR, VCCO = 1.80, TERM = NONE, DIR =
INPUT, DRIVE_STR = NR
gmii_rx_clk
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

Does someone know what happened and how to correct the errors?

 

Regards,

Sophia

 

0 Kudos
1 Reply
venkata
Moderator
Moderator
1,745 Views
Registered: ‎02-16-2010

Check the pins available in the device available in Zybo board at the link below.
https://www.xilinx.com/support/packagefiles/z7packages/xc7z010clg400pkg.txt

Verify the pinouts in your .xdc file against the available pin locations to understand the error.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos