Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎07-14-2016

THREAD ID (AXI - arm R5)

HI , 

The AXI interconnect logic between the AXI master and AXI slave might add extra bits to the AWID, ARID and WID signals generated by the AXI master so that it can route any responses from the final slave on the R or B channels back to the correct AXI master, but those additional ID bits would not be seen by the AXI master, only the AXI slave.I call those ID threads .


How id thread is formed ?

I cant understand exactl what bits added to the ID from the interface ,

If i want to simiulate in vivado a programm that will saw me how thread id is changing , how sould i impement that ? Any ideas ?

(I am a starter with vivado)


Thank you



0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎08-02-2011



Why do you want to do this? From the user perspective, the extra ID bits are totally internal to the AXI Interconnect and not exposed at any interface.


If you really want to, you could just simulate it and push down to the crossbar to see its ID bits. At the level of hierarchy of the crossbar, they are exposed at the interface.
0 Kudos