The AXI interconnect logic between the AXI master and AXI slave might add extra bits to the AWID, ARID and WID signals generated by the AXI master so that it can route any responses from the final slave on the R or B channels back to the correct AXI master, but those additional ID bits would not be seen by the AXI master, only the AXI slave.I call those ID threads .
How id thread is formed ?
I cant understand exactl what bits added to the ID from the interface ,
If i want to simiulate in vivado a programm that will saw me how thread id is changing , how sould i impement that ? Any ideas ?