05-30-2015 06:00 PM
I am using Vivado with AXI DMA and custom IP . I am facing the problem in Tlast. I have set the Tlast signal according to my output. In ILA , i can see perfect position for Last signal and also the correct output of my IP. But i see nothing in S2MM port of DMA. It means that DMA is not sending anything and not accepting data from my IP as it tlast signal of DMa (S2MM_WLAST ) is also zero on the wavefrom. Signals from my custom Ip are all right but S2MM channel is not working.
I have read in the documentation :
"The TVALID and TREADY handshake determines when information is passed across the interface. A two-way flow control mechanism enables both the master and slave to control the rate at which the data and control information is transmitted across the interface. For a transfer to occur both the TVALID and TREATY signals must be asserted. Either TVALID TREATY can be asserted first or both can be asserted in the same ACLK cycle.A master is not permitted to wait until TREADY is asserted before asserting TVALID. Once TVALID is asserted it must remain asserted until the handshake occurs.A slave is permitted to wait for TVALID to be asserted before asserting the corresponding TREADY. If a slave asserts TREADY, it is permitted to deassert TREADY before TVALID is asserted. The following sections give examples of the handshake sequence."
As i can only control M_AXIS_TVALID and M_AXIS_TLAST signal , so this is what i have done in my FPGA code and can see the perfect result for those ports of my IP. Can anyone please explain me how to assert TReady signal for DMA in my FPGA code so that it can accept M_AXIS_Tdata from my IP
I hope i explain well my problem . Kindly do me a favor. I have been stuck on this issue for a month and tried so much thing to resolve this but couldnt succeed.
05-30-2015 06:16 PM
I don't think that TREADY is the issue here because it looks to be always high, indicating that data is being transfered on each cycle when TVALID is asserted. However on the cycle when TLAST is asserted, TVALID is zero. The AXI slave will only look at TLAST on a cycle where TVALID is also asserted. TLAST should be asserted on the same cycle when you transfer the last data from the master, not on a cycle later.
05-30-2015 06:30 PM
Thanks for clarification. I had done that particular thing before but wants to get a data after Tvalid sets to zero even. Ok thats clear alot that i cant do such stuff ..
after posting this question, I have changed my FPGA code already to set tlast at the transferring of last data from IP. Hope now DMA will accept that data. After 10 minutes approx, i will be able to see my waveform after generating bitstream: will update you .
Thanks again for your reply.
05-30-2015 07:45 PM
what's the relationship between dynamic_0_m_axis_tready and dma0_mm2s_tready? can you post your block diagram ?
also you master interface is there a strobe signal ? if yes, are you controlling it?
05-30-2015 08:01 PM - edited 05-30-2015 08:03 PM
Well ; confusion was cleared. i was doing right things before but not sure about that relationship between valid and tlast, but thanks to @gszakacs ; he confirmed me that problem.
Now it is working perfectly.
But @muzaffer before this , i had written M_AXIS_TLAST <= S_AXIS_TLAST; and then i used floating_point operator which will take M_AXIS_TDATA and convert it into float and pass to DMA S2MM port. That had also perfect output.
But after now controlling M_AXIS_TLAST in fpga code as suggested above, my float output is completely different now.
But output is perfect if i remove floating_point operator.
i had set "tlast "option in floating point as well as "blocking " mode in flow control .
What can be the issue for unexpected behavior of floatingpoint operator IP.
And i had just connected DMA port (MM2S ) with S_AXIS of IP ; (S2MM ) with M_AXIS of IP . nothing different :)
05-23-2017 07:11 AM
"The AXI slave will only look at TLAST on a cycle where TVALID is also asserted. "
Is it correct ?
REF: AMBA® 4 AXI4-Stream Protocol Version: 1.0 Specification
2.5.1 Transfer with zero data or position bytes
A transfer can have TLAST asserted but contain no data or position bytes. This can be used to:
• indicate the end of a packet when there are no more data or position bytes to transmit
• push through any data that is held in intermediate buffers
• complete an operation at an end-point that is expecting a TLAST at the end of a packet.
A transfer that has TLAST asserted, but does not have any data or position bytes, can be merged
with an earlier transfer with matching TID and TDEST values that does not also have TLAST
asserted. See Merging considerations on page 2-6.
Because reordering is not supported, sending a transfer with zero data bytes will effectively push
through all transfers between a master and slave. See Transfer ordering on page 4-3.
05-23-2017 09:08 AM
@kokoz yes it is correct. If you notice the section you quote is talking about a "transfer" and it never mentions tvalid. A transfer is defined by tvalid & tready at the same time and 2.5.1 only talks about tlast in a transfer where all byte enables, keeps etc are turned off but tlast is on.