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kbj1213
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Registered: ‎08-25-2015

The mean of number of LUT

Hi, I'm a beginner for designing digital system on FPGA.

 

I have a question about the result of synthesis.

 

When I designed a simple 15bit 2 input adder or 11bit 3 input adder, 

 

the schematic of synthesis result had LUT6, LUT2, CARRY4 blocks.

 

I know that what LUT roles in adder.

 

I wonder the meaning of the number at LUT name. (like 6 in LUT6 , 2 in LUT2, 4 in CARRY4).

 

What the numbers do exactly mean?

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hbucher
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Registered: ‎03-22-2016

@kbj1213

Look at UG623 page 71 https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/virtex6_hdl.pdf

LUT6 Primitive: 6-Input Lookup Table with General Output

LUT2 Macro: 2-Bit Look-Up Table with General Output

CARRY4 Primitive: Fast Carry Logic with Look Ahead

This is for Virtex6. Look the respective doc for your device.

After you elaborate your design you can look at the Device graph and zooming in you can see these primitives.

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florentw
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Registered: ‎11-09-2015

Hi @kbj1213,

 

To add from @hbucher:

Recent Xilinx FPGAs (as 7-series) have LUT6 hardware primitives. LUT6 are 6-inputs LUTs. These LUT6 con be configured as 2 LUT5 with common inputs:

LUT6.JPG

 

In case of a LUT2/LUT3/LUT4 after synthesis, you will use a LUT6 or a LUT5 (as this is what you have, LUT2/3/4 does not really exists in the latest FPGAs) but to realize the functionality of a LUT2/3/4 (you will have unused inputs port, i.e. you won't use the LUT at its maximum capacity). This is the reason why on @hbucher image, LUT2/3/4 are instantiated using MACROs not PRIMITIVES directly (used to instantiate directly the HW).

 

The CARRY4 block is only the carry chain block present in the configurable logic blocks (CLBs).

 

For more information, you can read UG474 - 7 Series FPGAs CLB User Guide and watch this video about the CLBs.

 

Hope that helps,

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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