Timing fail for 64 bit division in fsm running @ 50MHz.
I want to do 64 bit division and square root operation within a fsm running at 50MHz. My current implementation has failed to obey timing constraints. I changed to implementation to expect the output of the division and square root operations after two clock cycles. That is, i added a dummy state to wait for the operation to complete. In other words, fsm will expect the result after 40 ns instead of 20ns. Is there any way to specify timing constraint for my fsm to expect output after 2 clock cycles ?.
The search term you need is "multi-cycle path". Searching for that and "ISE" or "Vivado" will bring up plenty of useful information for how to specify a multi-cycle path in whichever tools you're using.
With that said, if this is the same combinational 64-bit divider you had before, I suspect that two cycles won't be enough.