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srinivasan
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Registered: ‎02-17-2017

To convert GPIOs to SPI controller in zynq

Dear Xilinx Community,

 

As I need 3 SPI controllers for my applications and I have already used the existing 2 SPI controllers in Zynq. I have  knowledge on how this can be done in linux kernel once bit stream is generated

 

But as I am newbie to vivado , could you please help me out with the following

 

1. For the 3rd SPI controller, is it possible to convert GPIOs to SPI??

 

2. Could you please let me know how to configure 4 gpio signals as spi_clk, spi_cs, spi_mosi, spi_miso in vivado?

 

Kindly do the needful as early as possible

Awaiting for your replies

Many Thanks in advance

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muzaffer
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Registered: ‎03-31-2012

@srinivasan do you want to use PS MIO or PL IO for the SPI pin? For PS MIO, as you note, there are only 2 spi controllers so your options are to implement a bit-banging spi controller in sw or add your device to an existing controller by extending the chip select logic (are you sure you need a 3rd controller and not more chip select pins?)

 

The other option is to use the PL IO for SPI pins and add a spi controller to the PL using fpga fabric. This very much looks like an existing controller to linux once you configure your device tree properly.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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srinivasan
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Registered: ‎02-17-2017

Thanks a lot for your quick responses,

 

I have two requirements

1. First Requirement: I need 3rd SPI controller and I am planning to implement a bit-banging spi controller in sw in linux and device tree, am planning to use 4 pins of gpio 0 bank (ps7-gpio@e000a000)

 

Could you please what are all the changes needs to be done for generating the bit stream or could you pls provide some example of how to configure gpio pins and map it to PL pins and how to we specify bank numbers in device tree for bit bang?

 

2. Second Requirement: Could you please let me know how use the existing controller by using chip select pins in vivado, device tree and linux kernel & pls let me know how this can be verified in the userspace

 

Kindly do the needful as early as possible

Awaiting for your replies

Many Thanks in advance

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srinivasan
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Registered: ‎02-17-2017

Could you pls provide inputs how pins/bits of existing GPIO module can be configured in vivado via EMIO or MIO, Because I dont want to use axi-gpio

 

 

Kindly do the needful as early as possible

Awaiting for your replies

Many Thanks in advance

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srinivasan
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Registered: ‎02-17-2017

Dear Community

 

1. I have used GPIO via MIO instead of MIO, as we dont require Quad spi for our application I am making use of those 4 pins as GPIO0_1, GPIO0_2, GPIO0_3 and GPIO0_4 for my SPI gpio bit bang driver in linux
 
So could you please let me know as a next step how this 4 gpios pins can be  mapped, declared and constrained in vivado in .vhd, .bd and .xdc with some example
 
2.So that I can configure of this 4 pins for SPI bit bang in devicetree and linux
 
Please let me know whether this way of configuring ie., GPIO as MIO and accessing it in linux is possible or not

 

 

Kindly do the needful as early as possible

Eagerly awaiting for your replies

 

Many Thanks in advance

GPIO_MIO1.png
MIO_GPIO.png
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srinivasan
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Registered: ‎02-17-2017

Hi,

 

Could you please let me know when I can get the replies for the above queries as am eagerly waiting for your inputs and have been stuck and unable to progress further without your inputs


Could you please correct me if I have missed anything in configuring the existing GPIO controller (am planing to use gpio0_0, gpio0_1, gpio0_2, gpio0_3)

 

I need to configure gpio0_0 --  input

gpio0_1 -- output

gpio0_2 -- output

gpio0_3 -- output

 

 

1.so modified the block design as in the attached snapshots

 

2. Could you please help me in getting system_top.vhd modified in the  attachment to get the connections to be done for the above gpio configuration???

 

 

3.Constraints file have modified
set_property PACKAGE_PIN L21 [get_ports {GPIO_SPI[0]}]
set_property PACKAGE_PIN L22 [get_ports {GPIO_SPI[1]}]
set_property PACKAGE_PIN J21 [get_ports {GPIO_SPI[2]}]
set_property PACKAGE_PIN J22 [get_ports {GPIO_SPI[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_SPI[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_SPI[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_SPI[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_SPI[3]}]

 

 

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srinivasan
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Registered: ‎02-17-2017

1. I tried modifying the system_top.vhd as per my knowledge & I have attached the snapshot of .bd and system_top.vhd

 

But am facing the error , could you please let me know why am facing this error

[Synth 8-1789] cannot update 'in' object gpio_spi_in ["/media/n008/SECONDDRIVE/local_workspace/svn_src/trunk/platform/zynq/rtl/system_top.vhd":441]
[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

 

 

2.xdc changes as below

 

# LEDs on FPGA module
set_property PACKAGE_PIN L21 [get_ports {GPIO_SPI_IN[0]}]
set_property PACKAGE_PIN L22 [get_ports {GPIO_SPI_OUT[1]}]
set_property PACKAGE_PIN J21 [get_ports {GPIO_SPI_OUT[2]}]
set_property PACKAGE_PIN J22 [get_ports {GPIO_SPI_OUT[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_SPI_IN[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_SPI_OUT[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_SPI_OUT[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_SPI_OUT[3]}]

 

Kindly do the needful as early as possible

Many Thanks in advance

Screenshot from 2017-03-16 13:03:24.png
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srinivasan
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Registered: ‎02-17-2017

Dear community

 

Could anybody pls reply atleast to the below queries,

 1. Generate Bit stream

Could you please let me know how to configure one of the GPIO -EMIO based pins as input as I have configured 3 pins as output and I need to configure one pin as input in GPIO-EMIO (what chages to be done in vhdl code)
 

2. Am trying to create the dummy node by adding the below entires in Device tree

    aliases {
        ethernet0 = &ps7_ethernet_0;
        i2c0 = &ps7_i2c_0;
        i2c1 = &ps7_i2c_1;
        serial0 = &ps7_uart_1;
        serial1 = &ps7_uart_0;
        spi0 = &ps7_spi_0;
        /*spi1 = &ps7_qspi_0;*/
        spi1 = &ps7_spi_1;
        spi_gpio = &spi_gpio;
    } ;

 

    spi_gpio: spi-gpio {
            compatible = "spi-gpio";
            #address-cells = <1>;
            #size-cells = <0>;
           /* ranges; */
            gpio-mosi = <&ps7_gpio_0 54 0>;
            gpio-miso = <&ps7_gpio_0 55 0>;
            gpio-sck  = <&ps7_gpio_0 56 0>;
            cs-gpios  = <&ps7_gpio_0 57 1>;

            num-chipselects = <1>;
            status = "ok";

             spidev@2 {
                    compatible = "linux,spidev";
                    reg = <0x0>;
                 /*   #address-cells = <1>; */
                /*    #size-cells = <0>; */
                    spi-max-frequency = <50000000>;
             };
    };


I have configured in kernel (CONFIG_SPI_GPIO=y)

After kernel bootup it throws the below error, is there any dependency on the bitstream because of being gpio's not configured properly??
spi_gpio spi-gpio: gpio-sck property not found

 

Kindly do the needful as early as possible

Awaiting for your replies

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srinivasan
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Registered: ‎02-17-2017

Hi muzaffer,

 

Any updates/inputs on my queries as am blocked for your inputs, as am waiting for your inputs for a quiet long time ?

 

Mainly I require two inputs from you

 

1. I have configured 4 pins as GPIO EMIO output, among this Is it possible to use part of GPIO EMIO pin as input, if yes how this configuration can be done in .vhdl. .bd and xdc changes, request you to provide some code snippet for the same

 

2. How to map this GPIO EMIO numbers in device tree as mentioned in previoulsy are the below pin mappings are correct in device tree??

 

            gpio-mosi = <&ps7_gpio_0 54 0>;
            gpio-miso = <&ps7_gpio_0 55 0>;
            gpio-sck  = <&ps7_gpio_0 56 0>;
            cs-gpios  = <&ps7_gpio_0 57 1>;

 

Please redirect it to respective person if you are not the concerned person for this query

 

Eagerly awaiting for your replies

 

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srinivasan
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Registered: ‎02-17-2017

Any updates on the above queries??
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