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Visitor dmitryldm
Visitor
43,803 Views
Registered: ‎03-29-2013

Total Negative Slack vs Worst Negative Slack

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What is the Total Negative Slack? How does it differ from the Worst Negative Slack? Thank you!

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Historian
Historian
63,169 Views
Registered: ‎01-23-2009

Re: Total Negative Slack vs Worst Negative Slack

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A minor clarification (and pet peeve of mine).

 

The "Worst Negative Slack (WNS)" reported by commands like report_timing_summary is actually the worst positive slack. If WNS is positive then it means that the path passes. If it is negative, then it means the path fails. So, this is really a misnomer.

 

The "Total Negative Slack (TNS)" is the sum of the (real) negative slack in your design. If 0, then the design meets timing. If it is a positive number, then it means that there is negative slack in the design (hence your design fails). It cannot be negative.

 

Going on, the "Worst Hold Slack (WHS)" is correct - it is the worst hold slack in the design. Like WNS if positive, it means the path passes, if negative it fails.

 

Conversely "Total Hold Slack (THS)" is also a misnomer. It is really the sum of the (real) negative hold slack. If zero, your design passes, if positive, your design fails.

 

Avrum

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Instructor
Instructor
43,799 Views
Registered: ‎08-14-2007

Re: Total Negative Slack vs Worst Negative Slack

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If you're talking about timing numbers during Place and Route, then the total negative

slack is the sum of the negative slack for all paths that fail any timing constraint.  This

is not a particularly usefule metric other than to tell you how far off you are from reaching

timing closure.

 

Worst case Negative slack is the most negative of any single slack of the paths that

failed any constraint.  Again, unless put into perspective (which constraint failed

and which path) it only serves to show how badly you missed timing closure.

-- Gabor
Historian
Historian
63,170 Views
Registered: ‎01-23-2009

Re: Total Negative Slack vs Worst Negative Slack

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A minor clarification (and pet peeve of mine).

 

The "Worst Negative Slack (WNS)" reported by commands like report_timing_summary is actually the worst positive slack. If WNS is positive then it means that the path passes. If it is negative, then it means the path fails. So, this is really a misnomer.

 

The "Total Negative Slack (TNS)" is the sum of the (real) negative slack in your design. If 0, then the design meets timing. If it is a positive number, then it means that there is negative slack in the design (hence your design fails). It cannot be negative.

 

Going on, the "Worst Hold Slack (WHS)" is correct - it is the worst hold slack in the design. Like WNS if positive, it means the path passes, if negative it fails.

 

Conversely "Total Hold Slack (THS)" is also a misnomer. It is really the sum of the (real) negative hold slack. If zero, your design passes, if positive, your design fails.

 

Avrum

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Visitor dmitryldm
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43,787 Views
Registered: ‎03-29-2013

Re: Total Negative Slack vs Worst Negative Slack

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Thanks! As for the WNS and TNS, are they for setup checks?

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Visitor dmitryldm
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Registered: ‎03-29-2013

Re: Total Negative Slack vs Worst Negative Slack

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For the same path, may the Setup and Hold check results be different for synthesized and implemented design?

 

I looked in the timing constraints for Synthesis and for Implementation... The only different is so that the implementation constraints has in/out ports mapping to the I/Os of the design. Is this the only different?

 

When the timing checks are done on the synthesized design, are the routing delays taking into account?

 

As for the synthesis phase, is this only a logic synthesis without mapping the gates/memories/etc into real cells of the device?

 

Thank you!

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Historian
Historian
43,779 Views
Registered: ‎01-23-2009

Re: Total Negative Slack vs Worst Negative Slack

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For the same path, may the Setup and Hold check results be different for synthesized and implemented design?

 

Yes. There are three (primary) stages to generating a design

  - Synthesis converts your RTL code to an interconnected netlist of cells (LUTs, FFs, etc...)

  - Placement maps those cells to physical locations on the FPGA die

  - Route maps the connections between the cells to physical routing channels on the FPGA die

 

The first operation is done as part of "Synthesize Design" and the last two as part of "Implement Design"

 

Until all three are done, "final" timing cannot be determined. However, the tools allow you to do estimated timing after before placement and before routing. During these passes, its impossible to know what the routing delays will be (because the placement and/or routing have not yet been done), so the tools use estimated delays.

 

So, the results at the different places can definitely be different.

 

I looked in the timing constraints for Synthesis and for Implementation... The only different is so that the implementation constraints has in/out ports mapping to the I/Os of the design. Is this the only different?

 

During synthesis, the location constraints on the I/O are irrelevent, and will be ignored (generating a warning). To avoid the warning, people often do not include them during the synthesis process.

 

Timing constraints are necessary for both processes. The goal is to have them be identical for both processes, but it isn't always possible. While they are getting better, the naming of some cells during synthesis are not the same as during implementation - it may be necessary to have different constraints to accomodate the naming differences (this is most often the case for exceptions like internal set_multicycle_path and set_max_delay commands). For simple create_clock, set_input_delay and set_output_delay (which should all be applied to ports of the design), it should be possible to use the same constraints (and hence the same XDC).

 

When the timing checks are done on the synthesized design, are the routing delays taking into account?

 

Since the design isn't placed and routed yet, "real" timing information for the routing delays is not yet available. However, the tool uses estimates based on fanout (and potentially other clues) for the routing delays.

 

As for the synthesis phase, is this only a logic synthesis without mapping the gates/memories/etc into real cells of the device?

 

After synthesis, your design is a netlist of gates/memories/etc... in the Xilinx technology. However, the cells have no location on the die. So, some RTL code may be implemented as 3 interconnected LUT6 cells, but we don't know which of the tens/hundreds of thousands of possible LUT6 locations on the die will be used for those 3 LUT6 cells. That will be determined in the implementation (placement) process.

 

Avrum

 

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Adventurer
Adventurer
28,319 Views
Registered: ‎07-18-2016

Re: Total Negative Slack vs Worst Negative Slack

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Hello,

 

In my design I am getting WNS as 31.178ns, WHS as 0.005ns and WPWS as 3.000ns. what does this means. should WNS, WHS, WPWS be more or less.

 

Thanks & Regards,

Rashmi

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Explorer
Explorer
28,300 Views
Registered: ‎11-25-2015

Re: Total Negative Slack vs Worst Negative Slack

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@rashmi_ha

 

The slacks are positive, it means your design is meeting timing requirements.

If any of them are negative, it means the design fails timing. From the numbers, your design is just meeting hold requirement and there is good margin for setup requirement.

 

Also, please post a new thread for a new query for better visibility of your post and tracking.

 

Regards,

Sravanthi