For the same path, may the Setup and Hold check results be different for synthesized and implemented design?
Yes. There are three (primary) stages to generating a design
- Synthesis converts your RTL code to an interconnected netlist of cells (LUTs, FFs, etc...)
- Placement maps those cells to physical locations on the FPGA die
- Route maps the connections between the cells to physical routing channels on the FPGA die
The first operation is done as part of "Synthesize Design" and the last two as part of "Implement Design"
Until all three are done, "final" timing cannot be determined. However, the tools allow you to do estimated timing after before placement and before routing. During these passes, its impossible to know what the routing delays will be (because the placement and/or routing have not yet been done), so the tools use estimated delays.
So, the results at the different places can definitely be different.
I looked in the timing constraints for Synthesis and for Implementation... The only different is so that the implementation constraints has in/out ports mapping to the I/Os of the design. Is this the only different?
During synthesis, the location constraints on the I/O are irrelevent, and will be ignored (generating a warning). To avoid the warning, people often do not include them during the synthesis process.
Timing constraints are necessary for both processes. The goal is to have them be identical for both processes, but it isn't always possible. While they are getting better, the naming of some cells during synthesis are not the same as during implementation - it may be necessary to have different constraints to accomodate the naming differences (this is most often the case for exceptions like internal set_multicycle_path and set_max_delay commands). For simple create_clock, set_input_delay and set_output_delay (which should all be applied to ports of the design), it should be possible to use the same constraints (and hence the same XDC).
When the timing checks are done on the synthesized design, are the routing delays taking into account?
Since the design isn't placed and routed yet, "real" timing information for the routing delays is not yet available. However, the tool uses estimates based on fanout (and potentially other clues) for the routing delays.
As for the synthesis phase, is this only a logic synthesis without mapping the gates/memories/etc into real cells of the device?
After synthesis, your design is a netlist of gates/memories/etc... in the Xilinx technology. However, the cells have no location on the die. So, some RTL code may be implemented as 3 interconnected LUT6 cells, but we don't know which of the tens/hundreds of thousands of possible LUT6 locations on the die will be used for those 3 LUT6 cells. That will be determined in the implementation (placement) process.
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