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Registered: ‎02-17-2017

Unable to configure the one of the GPIO pin as input _(PS GPIO to EMIO ) in Zynq

Dear Xilinx Community,



I have already enabled in and configured in re-customize ip with width as 4 in EMIO GPIO (width)

I need 3 gpio pins as output and one pin as input, Could you please let me know how to configure one of the GPIO pins as input among the 4. Could you please provide some vhdl code snippet or is there anyways that can be done in "Re-customize IP",


Could anybody please let me know whether this can be done in vivado ?

As am using linux BSPs or Is it possible to configure the one of the GPIO as input direction in device tree , could you please provide some example for the same??


Kindly do the needful as early as possible

Many Thanks in advance

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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎08-01-2008

In Vivado Design Suite  bidirectional means that there is an input, an output, and a tristate signal which can connect to an IOBUF primitive so that you can select which direction the GPIO is intended to go.

In block design, you can enable EMIO GPIO from the PS7 IP configuration window which enables a set of EMIO GPIO ports (likely named GPIO_0) on the PS7 block.

You can then right click on that GPIO_0 port (all of the wires are grouped together) and select "Make External" to create an external port for them and automatically connect wires to the external port. I like to name my EMIO GPIO ports "emio_user" since I usually connect them to the user LEDs, DIP switches, and Push Buttons of a board for demos.

That's it!

check this ARs


When you create the wrapper for the block design, Vivado automatically picks up on the GPIO_I, GPIO_O, and GPIO_T signals and tries to pack them into IOBUF primitives for you, like this:

emio_user_tri_iobuf_8: component IOBUF
port map (
I => emio_user_tri_o_8(8),
IO => emio_user_tri_io(8),
O => emio_user_tri_i_8(8),
T => emio_user_tri_t_8(8)

Now all you need to do is to make sure that you have the matching constraints for those external nets and you have bidirectional ports.


Thanks and Regards
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Registered: ‎07-31-2012



Alternate method is as explained below for EMIO similar to MIOs


There are two approach of accessing PS EMIO one is post linux boot and using through sysfs to control direction, value. Alternatively, devemem command can be used as well on PS GPIO register to do the same.
Another approach non linux is register level  to configure GPIO can be done through memory read /write to its appropriate register in SD-XSDB using mwr/mrd commands.
Example: Configure MIO pin 10 as an output
1. Set the direction as output: Write 0x0000_0400 to the gpio.DIRM_0 register.
2. Set the output enable: Write 0x0000_0400 to the gpio.OEN_0 register.
Note: The output enable has significance only when the GPIO pin is configured as an output.

For GPIO pins configured as outputs, there are two options to program the desired value.

Option 1: Read, modify, and update the GPIO pin using the gpio.DATA_0 register.
Example: Set GPIO output pin 10 using the DATA_0 register.
1. Read the gpio.DATA_0 register: Read gpio.DATA_0 register to the reg_val variable.
2. Modify the value: Set reg_val [10] =1.
3. Write updated value to output pin: Write reg_val to the gpio.DATA_0 register.

Option 2: Use the MASK_DATA_x_MSW/LSW registers to update one or more GPIO pins.
Example: Set output pins 20, 25, and 30 to 1 using the MASK_DATA_0_MSW register.
1. Generate the mask value for pins 20, 25, and 30: To drive pins 20, 25 and 30, 0xBDEF is the
mask value for gpio.MASK_DATA_0_MSW [MASK_0_MSW].
2. Generate the data value for pins 20, 25, 30: To drive 1 on pins 20, 25, and 30, 0x4210 is the
data value for gpio.MASK_DATA_0_MSW [DATA_0_MSW].
3. Write the mask and data to the MASK_DATA_x_MSW register: Write 0xBDEF_4210 to the
gpio.MASK_DATA_0_MSW register.



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