Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎04-13-2017

Unable to program a SPI flash via Artix 7 (XC7A35T)



as mentioned in the subject I'm trying to program a Spansion S25FL064P0XNFI001 via an Artix 7 XC7A35TFTG256. The EEPROM is connected via SPI with the FPGA. For programming I use JTAG and the Xilinx Platform Cable USB II.


I've attached the used constraint file to configure the SPI bus (text.xdc) as well as the schematics section of the Artix 7 and EEPROM connections. 


The board is configured in MASTER SPI mode and shows the following behavior:


After starting the board the FPGA starts to distribute a 3 MHz clock via the CCLK_0 PIN.The FCS, DIN and MOSI PINs are on 'low' voltage level. The W_B and Hold_B PINs of the EEPROM are 'high'.


When I try to program a memory configuration file (*.mcs or *.bin) with Vivado 2016.4, Vivado stops after a few seconds and shows the following message: '[Labtools 27-2251] Unable to read device properties. Please make sure that the proper configuration memory part is selected'. But within Vivado I've choosen the s25fl064p as memory part which is the alias device for the S25FL064P0XNFI001 (UG908, appendix C).


During the program progress of the EEPROM the FPGA rises the FCS PIN to 'high', then it stops the clock and turns CCLK_0 to 'low'. There is no signal transfer on the DIN and MOSI PIN (J14 and J13 of the package) and no voltage change of the W_B and Hold_B PINs (like expected).

First, I thought that J14 and J13 are not working, but I can configure these PINs as well as other IO-PINs of the FPGA and the PIN behave like expected.


I've tried x1, x2 and x4 SPI configuration. All configurations are showing the same behavior.


In a similar post, it is mentioned that VCCBRAM has not the correct voltage and might cause such an error. In my case VCCBRAM is not an issue.  

connection FPGA Flash.jpg
0 Kudos
1 Reply
Registered: ‎03-31-2016

Hi, I had almost the same problem. What i learned is that signal integrity on the JTAG interface is very critical, so care must be taken to properly terminate and route the interface signals on the board. I could not see the bottom part of your schematic for the JTAG interface, so I am attaching what works for me. The RC termination on the TCK line is critical. Other thing you can try is to slow down the interface speed of JTAG fro default 6MHz to 3MHz or even 1.5MHz. Hope this helps.
Xilinx_JTAG Config.JPG
0 Kudos