cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
l.enoal
Visitor
Visitor
4,147 Views
Registered: ‎06-01-2015

Use one regsiter per slice

Jump to solution

Hello,

 

I use a kintex 7 XC7K70T consist of 8 registers per slice and i would like to know if it's possible to contrain the implement design in ISE to use one regsiter per slice.

 

Thank you.

0 Kudos
1 Solution

Accepted Solutions
anusheel
Moderator
Moderator
7,773 Views
Registered: ‎07-21-2014

@l.enoal

 

Best way is to open the design in PlanAhead and create a Pblock for the targeted module/cells, this will tell the tool to place the logic within the Pblock(area selected in device). In case you don’t want to use PlanAhead for further flow, simply imoprt the PlanAhead generated constraints in ISE.

 

Regarding FF/Slice related query, you need to write a script which can write LOC/BEL constraint for the desired FFs. This way you can place the FFs in Slices as per your requirement.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

 

View solution in original post

0 Kudos
6 Replies
syedz
Moderator
Moderator
4,144 Views
Registered: ‎01-16-2013

@l.enoal,

 

Just curious, Why would you wana implement only one regiister per slice? 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
syedz
Moderator
Moderator
4,140 Views
Registered: ‎01-16-2013

@l.enoal,

 

May be you can try with Unique control signals (Clock, CE and SR)  for Each register so that they are placed in different Slice.

 

Check this AR#24667

http://www.xilinx.com/support/answers/24667.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
anusheel
Moderator
Moderator
4,132 Views
Registered: ‎07-21-2014

@l.enoal

 

Yes, you can lock them manually if you are targeting less number of registers.

I guess there is no global switch for this requirement. Also, if the flops are using different control signals then by default tool has to place them in different slices.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

0 Kudos
l.enoal
Visitor
Visitor
4,124 Views
Registered: ‎06-01-2015

Thank you for your answers.

 

So, if I understand there aren't options into ISE softawre to force the implement design use one register per slice. And with FPGA Editor or Floorplan it isn't possible? Because in my code all regsiters don't use the same control sets.

 

And also, is it possible to choose the slices that we want use with the tools of ISE. For example if I want just use a part of chip and not all chip.

 

Best Regards

0 Kudos
nagabhar
Xilinx Employee
Xilinx Employee
4,120 Views
Registered: ‎05-07-2015

HI @l.enoal

 

You can use AREA_GROUP constraints  (pblocks in PLanahead), to constraint a part of your design to a particular region of the device.
refer page 46 of  contraint guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf

Thanks
Bharath
--------------------------------------------------​--------------------------------------------
Please mark the Answer as "Accept as solution" if information provided addresses your query/concern.
Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
anusheel
Moderator
Moderator
7,774 Views
Registered: ‎07-21-2014

@l.enoal

 

Best way is to open the design in PlanAhead and create a Pblock for the targeted module/cells, this will tell the tool to place the logic within the Pblock(area selected in device). In case you don’t want to use PlanAhead for further flow, simply imoprt the PlanAhead generated constraints in ISE.

 

Regarding FF/Slice related query, you need to write a script which can write LOC/BEL constraint for the desired FFs. This way you can place the FFs in Slices as per your requirement.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

 

View solution in original post

0 Kudos