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Participant gtushar
Participant
2,919 Views
Registered: ‎02-08-2016

VCU110 evaluation board GTH placement issue

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I am using the evaluation board, VCU110 and I want to use the GTH transceiver of the Virtex Ultrascale FPGA.

 

The GT Channel is placed in Quad 220 location X0Y4 and the reference clock is coming from Quad 221, for this reason, I am trying to place GT COMMON at location X0Y8 but Vivado is throwing me an error which says:

 

" Unroutable Placement! A GTHE_COMMON / GTHE_CHANNEL clock component pair is not placed in a routable site pair. The GTHE_COMMON component can use the dedicated path between the GTHE_COMMON and the GTHE_CHANNEL if both are placed in the same clock region. If this sub-optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_gt_common_block/ten_gig_eth_pcs_pma_gt_common_wrapper_i/common_inst/qpll0outclk] > "

 

here is the content of the XDC:

set_property LOC GTHE3_COMMON_X0Y8 [get_cells -hier -filter {NAME=~ ten_gig_eth_pcs_pma_core_support_layer_i/ten_gig_eth_pcs_pma_gt_common_block/*gthe3_common*}]
set_property LOC GTHE3_COMMON_X0Y8 [get_cells -hier -filter {NAME=~ ten_gig_eth_pcs_pma_core_support_layer_i/*shared*ibufds_inst}]
set_property LOC GTHE3_CHANNEL_X0Y4 [get_cells -hierarchical -filter {NAME =~ *gen_channel_container[1].*gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]

 

Has anyone tried to place a GTH on VCU110 evaluation board?

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Xilinx Employee
Xilinx Employee
5,487 Views
Registered: ‎02-06-2013

Re: VCU110 evaluation board GTH placement issue

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Hi

 

Set the GT Common location to X0Y1 and just allocate the reference clock pins to bank 221 locations(AK12,AK13 or AL10,AL11) and the tool will take care of the connections.

 

 

Regards,

Satish

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3 Replies
Xilinx Employee
Xilinx Employee
5,488 Views
Registered: ‎02-06-2013

Re: VCU110 evaluation board GTH placement issue

Jump to solution

Hi

 

Set the GT Common location to X0Y1 and just allocate the reference clock pins to bank 221 locations(AK12,AK13 or AL10,AL11) and the tool will take care of the connections.

 

 

Regards,

Satish

--------------------------------------------------​--------------------------------------------
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Participant gtushar
Participant
2,895 Views
Registered: ‎02-08-2016

Re: VCU110 evaluation board GTH placement issue

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@yenigal

Do I also need to map the refclk as the SOUTHCLK of GT_COMMON ?

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Xilinx Employee
Xilinx Employee
2,890 Views
Registered: ‎02-06-2013

Re: VCU110 evaluation board GTH placement issue

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Hi

 

The tool will take care of the mapping and no need to explicitly map to the south clock.

Regards,

Satish

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