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Visitor markfarnell
Visitor
2,970 Views
Registered: ‎05-02-2017

VCU118 developmental board fails the VCU118 setup test in XTP439

I have just purchased the Xilinx Virtex UltraScale+ VCU118 development board:

 

https://www.xilinx.com/products/boards-and-kits/ek-u1-vcu118-es1-g.html

 

Then I followed the XTP453 quick start guide instruction, and successfully completed the self-test, and the board passes the test.

 

I followed the instructions in XTP449 and connect everything up, including the JTAG, UART, ethernet, PCIe loopback. and radio loopback.

 

I subsequently followed the XTP439 instructions, and downloaded the BIT test program.  However, it fails the "VCU118 SETUP" test with the log:

 

Info: VCU118 SETUP test started...

Info: The test will take 0 hours, 01 minutes, and 37 seconds. 0:01:37

Info: This step started at: 2017-05-04 16:01:42

step finished

Error: 'comm' type in step 0 never found a serial port to connect to in test 0

Info: This step started at: 2017-05-04 16:01:42

Error: Stopped because step 0 failed in test 0

Info: Result for step 0: Fail
Info: The test took 0 hours, 00 minutes, and 00 seconds. 0:00:00

 

However, I was able to reset the board default firmware using XTP445, and both factory-loaded designs worked after reflashing.  Therefore I can conclude that JTAG works.

 

On the device manager, these ports are listed:

 

Communication Port (COM1)

Silicon Labs Dual CP2105 USB to UART Brudge Enhanced COM port (COM4)

Silicon Labs Dual CP2105 USB to UART Standard Enhanced COM port (COM5)

USB Serial Port (COM3)

 

 

I am running Microsoft Windows 10.0.

 

So what else could go wrong and how can I fix it?

 

Thanks!

 

 

 

 

 

 

 

 

0 Kudos
4 Replies
Xilinx Employee
Xilinx Employee
2,961 Views
Registered: ‎04-16-2012

Re: VCU118 developmental board fails the VCU118 setup test in XTP439

Hi @markfarnell

 

Here is an answer record that discuss about the same issue: https://www.xilinx.com/support/answers/68521.html

 

Thanks,

Vinay

--------------------------------------------------------------------------------------------
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Visitor markfarnell
Visitor
2,916 Views
Registered: ‎05-02-2017

Re: VCU118 developmental board fails the VCU118 setup test in XTP439

I did that modification specified in:

 

https://www.xilinx.com/support/answers/68521.html

 

for vcu118_bit/scui/config.json.  I also ran SCUI.exe, and it can successfully get all information.

 

However, when I tried to run BIT.exe, the VCU118 setup step still fails with the same message:

 

Error: 'comm' type in step 0 never found a serial port to connect to in test 0

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Xilinx Employee
Xilinx Employee
2,905 Views
Registered: ‎11-13-2014

Re: VCU118 developmental board fails the VCU118 setup test in XTP439

Hi @markfarnell,

 

The instructions in AR 68521 apply only to the SCUI tool (if you notice the config.json is local to the SCUI.exe executable).  Those instructions will not directly apply to the BIT as the two are separate applications.

 

I've been tracking this issue for a while, and what we've found so far is that the newest version of the Silicon labs driver (6.7.4) does not appear work correctly with the BIT.  There is active development looking into the root cause but for now if you are looking to get the BIT up and running, you might need to install an older version of the Si Labs Driver.

 

You can check which version of the driver is installed by opening the Windows device manager and right clicking on one of the virtual COM ports, then selecting the "Driver" tab.  My guess is that the latest version was installed by default.

 

device_manager.PNG

driver_version.PNG

 

 

If you find that you have 6.7.4 installed, you might try installing an older version from the Si Labs website:

http://www.silabs.com/products/development-tools/software/usb-to-uart-bridge-vcp-drivers

 

If I look at my PC with a VCU118 connected, I see that I have version 6.7.2 of the Si Labs driver and, that the BIT is able to connect and run.

 

vcu118_bit.PNG

 

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Visitor markfarnell
Visitor
2,883 Views
Registered: ‎05-02-2017

Re: VCU118 developmental board fails the VCU118 setup test in XTP439

Thank you very much for your advice.  After I removed the 6.7.2 driver, I realized that my Windows 10 actually comes with the 6.7.1 driver, which works out of the box.

 

So could you please update the documentation and manuals and stress that 6.7.4 will not work, and provide a copy of the 6.7.2 driver on the Xilinx site?

 

I have re-run the BIT test, the VCU118 test passes, but the BIST test at the bottom fails with:

 

 

Info: BIST test started...

Info: The test will take 0 hours, 01 minutes, and 15 seconds. 0:01:15

Info: This step started at: 2017-05-05 11:45:22

Info: This step started at: 2017-05-05 11:45:22

****** Vivado v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source {tcl\vcu118_ipi.tcl}
# open_hw
# connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2017.1
**** Build date : Apr 14 2017-19:11:07
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

 


# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
# set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# set_property PROGRAM.FILE {[pwd]/../bitstream/ipi_app.bit} [lindex [get_hw_devices] 0]
# program_hw_devices [lindex [get_hw_devices] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 276.238 ; gain = 1.012
# close_hw_target [current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]]
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# disconnect_hw_server localhost:3121
# close_hw
***********************************************************
***********************************************************
** Xilinx UltraScale FPGA VCU118 Evaluation Kit IPI Test **
***********************************************************
***********************************************************

Choose Feature to Test:
1: UART Test
2: LED Test
3: IIC Test
5: TIMER Test
7: SWITCH Test
9: DDR4 External Memory Test
A: BRAM Internal Memory Test
B: BUTTON Test
C: Clocking Test
D: PMOD Test
F: LVDS Test
G: System Monitor Test
0: Exit
****** Webtalk v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-1052-sc-cs-371166/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] 'D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-1052-sc-cs-371166/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Fri May 5 11:45:52 2017. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.1/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Fri May 5 11:45:52 2017...
INFO: [Common 17-206] Exiting Vivado at Fri May 5 11:45:52 2017...
step finished

Info: This step started at: 2017-05-05 11:45:53
Writing: '33'

Info: This step started at: 2017-05-05 11:45:54
3

*************************************************************
** VCU118 USER Si570 1 IIC EEPROM Test
*************************************************************
Calling iic_read

Reading EEPROM data from USER Si570 1

ReadBuffer[00] = 0x01
ReadBuffer[01] = 0xC2
ReadBuffer[02] = 0xBC
ReadBuffer[03] = 0x01
ReadBuffer[04] = 0x29
ReadBuffer[05] = 0x91
ReadBuffer[06] = 0x07
ReadBuffer[07] = 0xC2
ReadBuffer[08] = 0xC0
ReadBuffer[09] = 0x00
ReadBuffer[10] = 0x00
ReadBuffer[11] = 0x00
ReadBuffer[12] = 0x00
ReadBuffer[13] = 0xC2
ReadBuffer[14] = 0xC0
ReadBuffer[15] = 0x00


VCU118 USER Si570 1 IIC EEPROM Test PASSED

*************************************************************
** VCU118 QSFP1 IIC EEPROM Test
*************************************************************
Calling iic_read

Reading EEPROM data from QSFP1
Writing: '55'

Info: This step started at: 2017-05-05 11:45:55
Writing: '99'

Info: This step started at: 2017-05-05 11:46:20
Writing: 'AA'

Info: This step started at: 2017-05-05 11:46:30
Writing: 'CC'

Info: This step started at: 2017-05-05 11:46:31
Writing: 'DD'

Info: This step started at: 2017-05-05 11:46:32
Writing: 'FF'

Info: This step started at: 2017-05-05 11:46:33
Writing: 'GG'

step finished

Error: Could not find regular expression in step 0 of test 11 - "(.*)All\s+Tests\s+Complete:\s+IIC\s+PASSED"

Error: Could not find regular expression in step 0 of test 11 - "(.*)Completed\s+IPI\s+Timer\s+Example"

Error: Could not find regular expression in step 0 of test 11 - "(.*)###\s+DDR4\s+Memory\s+Test\s+finished\s+successfully\s+###"

Error: Could not find regular expression in step 0 of test 11 - "(.*)AXI\s+BRAM\s+test\s+iteration\s+#1\s+has\s+PASSED!"

Error: Could not find regular expression in step 0 of test 11 - "(.*)Clocking\s+Test\s+Passed"

Error: Could not find regular expression in step 0 of test 11 - "(.*)PMOD\s+Test\s+passed"

Error: Could not find regular expression in step 0 of test 11 - "(.*)FMC\s+LVDS\s+Test\s+passed"

Error: Could not find regular expression in step 0 of test 11 - "(.*)System\s+Monitor\s+Example\s+passed!"

Error: Could not find regular expression in step 0 of test 11 - "(.*)The\s+Current\s+Temperature\s+is\s+[3-4]\d.\d\d\d\s+Centigrades"

Info: Result for step 0: Fail
Info: Result for step 1: Pass
Info: Result for step 2: Fail
Info: Result for step 3: Fail
Info: Result for step 4: Fail
Info: Result for step 5: Fail
Info: Result for step 6: Fail
Info: Result for step 7: Fail
Info: Result for step 8: Fail
Info: Result for step 9: Fail

Info: The test took 0 hours, 01 minutes, and 22 seconds. 0:01:22

 

 

 

 

 

 

 

 

 

 

 

Also, the IBERT QSFP fails with:

 

Info: IBERT QSFP Bottom test started...

Info: The test will take 0 hours, 03 minutes, and 53 seconds. 0:03:53

Info: This step started at: 2017-05-05 11:52:58

****** Vivado v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source {tcl\vcu118_ibert_bank_qsfp1.tcl}
# open_hw
# connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2017.1
**** Build date : Apr 14 2017-19:11:07
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

 


# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
# set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
# open_hw_target -jtag_mode 1
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
INFO: [Labtoolstcl 44-467] Setting hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331 into jtag_mode
# scan_ir_hw_jtag 6 -tdi 0b
# scan_ir_hw_jtag 6 -tdi 3f
# close_hw_target
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# set_property PROGRAM.FILE {[pwd]/../bitstream/ibert_bank_all.bit} [lindex [get_hw_devices] 0]
# current_hw_device [lindex [get_hw_devices] 0]
# refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1435] Device xcvu9p (JTAG device index = 0) is not programmed (DONE status = 0).
# program_hw_devices [lindex [get_hw_devices] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 409.582 ; gain = 2.090
# close_hw_target [current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]]
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# disconnect_hw_server
# close_hw
****** Webtalk v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-9252-sc-cs-371166/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] 'D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-9252-sc-cs-371166/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Fri May 5 11:53:58 2017. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.1/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Fri May 5 11:53:58 2017...
INFO: [Common 17-206] Exiting Vivado at Fri May 5 11:53:58 2017...
step finished

Info: This step started at: 2017-05-05 11:53:58

****** Vivado v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source {tcl\vivado_ibert_reset.tcl}
# open_hw
# catch {disconnect_hw_server localhost:3121}
# connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
# set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# current_hw_device [lindex [get_hw_devices xcvu9p_0] 0]
# refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcvu9p_0] 0]
INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 IBERT core(s).
# set_property PORT.QPLL0RESET 1 [get_hw_sio_commons *];
# commit_hw_sio [list [get_hw_sio_commons {*}] ]
# set_property PORT.QPLL0RESET 0 [get_hw_sio_commons *];
# commit_hw_sio [list [get_hw_sio_commons {*}] ]
# set_property PORT.QPLL1RESET 1 [get_hw_sio_commons *];
# commit_hw_sio [list [get_hw_sio_commons {*}] ]
# set_property PORT.QPLL1RESET 0 [get_hw_sio_commons *];
# commit_hw_sio [list [get_hw_sio_commons {*}] ]
# set_property PORT.CPLLRESET 1 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# set_property PORT.CPLLRESET 0 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# set_property PORT.GTRXRESET 1 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# set_property PORT.GTRXRESET 0 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# set_property PORT.GTTXRESET 1 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# set_property PORT.GTTXRESET 0 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# refresh_hw_sio [get_hw_sio_gts *]
# refresh_hw_sio [get_hw_sio_commons *]
# close_hw_target [current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]]
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
close_hw_target: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 611.023 ; gain = 0.000
# disconnect_hw_server localhost:3121
# close_hw
****** Webtalk v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-10336-sc-cs-371166/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] 'D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-10336-sc-cs-371166/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Fri May 5 11:54:27 2017. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.1/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Fri May 5 11:54:27 2017...
INFO: [Common 17-206] Exiting Vivado at Fri May 5 11:54:27 2017...
step finished

Info: This step started at: 2017-05-05 11:54:27

****** Vivado v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source {tcl\vcu118_ibert_bank_qsfp1_status.tcl}
# open_hw
# catch {disconnect_hw_server localhost:3121}
# connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
# set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# current_hw_device [lindex [get_hw_devices xcvu9p_0] 0]
# refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0]
INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 IBERT core(s).
refresh_hw_device: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 602.863 ; gain = 327.676
# set xil_newLinks [list]
# set xil_newLink [create_hw_sio_link -description {Link 0} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y48/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y48/RX] 0] ]
# lappend xil_newLinks $xil_newLink
# set xil_newLink [create_hw_sio_link -description {Link 1} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y49/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y49/RX] 0] ]
# lappend xil_newLinks $xil_newLink
# set xil_newLink [create_hw_sio_link -description {Link 2} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y50/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y50/RX] 0] ]
# lappend xil_newLinks $xil_newLink
# set xil_newLink [create_hw_sio_link -description {Link 3} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y51/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y51/RX] 0] ]
# lappend xil_newLinks $xil_newLink
# set xil_newLinkGroup [create_hw_sio_linkgroup -description {Link Group 0} [get_hw_sio_links $xil_newLinks]]
# unset xil_newLinks
# set_property TX_PATTERN {PRBS 31-bit} [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property RX_PATTERN {PRBS 31-bit} [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property TXPRE {2.21 dB (01001)} [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property TXPOST {6.02 dB (10100)} [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property TXDIFFSWING {254 mV (00010)} [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.TX_RESET_DATAPATH 1 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.TX_RESET_DATAPATH 0 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.RX_RESET_DATAPATH 1 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.RX_RESET_DATAPATH 0 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.MGT_ERRCNT_RESET_CTRL 1 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.MGT_ERRCNT_RESET_CTRL 0 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcvu9p_0] 0]
INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 IBERT core(s).
# refresh_hw_sio [list [get_hw_sio_links {localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y48/TX->localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y48/RX}] ]
# refresh_hw_sio [list [get_hw_sio_links {localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y49/TX->localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y49/RX}] ]
# refresh_hw_sio [list [get_hw_sio_links {localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y50/TX->localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y50/RX}] ]
# refresh_hw_sio [list [get_hw_sio_links {localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y51/TX->localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_231/MGT_X1Y51/RX}] ]
# puts "Waiting 120 seconds for test to run."
Waiting 120 seconds for test to run.
# after [expr 120 * 1000]
# set offset 40
# set initial_links 0
# for {set i $offset} {$i <= 43} {incr i} {
# set j [expr {$i - $offset + $initial_links}]
# set display_name [get_property {DISPLAY_NAME} [lindex [get_hw_sio_gts] $i]]
# set quad_name [lindex [split [get_property {NAME} [lindex [get_hw_sio_gts] $i]] /] 6]
# set qpll0 [expr [expr $i / 4] * 6]
# #set qpll1 [expr [expr [expr $i / 4] * 6] + 1]
# #set cpll0 [expr $qpll0 + 2 + [expr $i%4]]
# puts "$quad_name:$display_name: DESCRIPTION=[get_property {DESCRIPTION} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: STATUS=[get_property {STATUS} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: QPLL0_STATUS=[get_property {QPLL0_STATUS} [lindex [get_hw_sio_plls] $qpll0]]"
# #puts "$quad_name:$display_name: QPLL1_STATUS=[get_property {QPLL1_STATUS} [lindex [get_hw_sio_plls] $qpll1]]"
# #puts "$quad_name:$display_name: CPLL_STATUS=[get_property {PLL_STATUS} [lindex [get_hw_sio_plls] $cpll0]]"
# puts "$quad_name:$display_name: LINE_RATE=[get_property {LINE_RATE} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: LOGIC.ERRBIT_COUNT=[get_property {LOGIC.ERRBIT_COUNT} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: RX_RECEIVED_BIT_COUNT=[get_property {RX_RECEIVED_BIT_COUNT} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: TX_PATTERN=[get_property {TX_PATTERN} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: RX_PATTERN=[get_property {RX_PATTERN} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: LOOPBACK=[get_property {LOOPBACK} [lindex [get_hw_sio_links] $j]]"
# # Debug lines to insure the correct alignment of the get_hw_sio_gts, get_hw_sio_links, and get_hw_sio_plls numbering
# puts "$quad_name:$display_name: TX_ENDPOINT=[get_property {TX_ENDPOINT} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: RX_ENDPOINT=[get_property {RX_ENDPOINT} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: NAME=[get_property {NAME} [lindex [get_hw_sio_gts] $i]]"
# puts "$quad_name:$display_name: get_hw_sio_plls=[lindex [get_hw_sio_plls] $qpll0]"
# #puts "$quad_name:$display_name: get_hw_sio_plls=[lindex [get_hw_sio_plls] $qpll1]"
# #puts "$quad_name:$display_name: get_hw_sio_plls=[lindex [get_hw_sio_plls] $cpll0]"
# }
Quad_231:MGT_X1Y48: DESCRIPTION=Link 0
Quad_231:MGT_X1Y48: STATUS=NO LINK
Quad_231:MGT_X1Y48: QPLL0_STATUS=LOCKED
Quad_231:MGT_X1Y48: LINE_RATE=28.102
Quad_231:MGT_X1Y48: LOGIC.ERRBIT_COUNT=0007328251A6
Quad_231:MGT_X1Y48: RX_RECEIVED_BIT_COUNT=62481179520
Quad_231:MGT_X1Y48: TX_PATTERN=PRBS 31-bit
Quad_231:MGT_X1Y48: RX_PATTERN=PRBS 31-bit
Quad_231:MGT_X1Y48: LOOPBACK=None
Quad_231:MGT_X1Y48: TX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y48/TX
Quad_231:MGT_X1Y48: RX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y48/RX
Quad_231:MGT_X1Y48: NAME=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y48
Quad_231:MGT_X1Y48: get_hw_sio_plls=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/COMMON_X1Y12/QPLL0
Quad_231:MGT_X1Y49: DESCRIPTION=Link 1
Quad_231:MGT_X1Y49: STATUS=NO LINK
Quad_231:MGT_X1Y49: QPLL0_STATUS=LOCKED
Quad_231:MGT_X1Y49: LINE_RATE=28.102
Quad_231:MGT_X1Y49: LOGIC.ERRBIT_COUNT=00077390C3EC
Quad_231:MGT_X1Y49: RX_RECEIVED_BIT_COUNT=63259471120
Quad_231:MGT_X1Y49: TX_PATTERN=PRBS 31-bit
Quad_231:MGT_X1Y49: RX_PATTERN=PRBS 31-bit
Quad_231:MGT_X1Y49: LOOPBACK=None
Quad_231:MGT_X1Y49: TX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y49/TX
Quad_231:MGT_X1Y49: RX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y49/RX
Quad_231:MGT_X1Y49: NAME=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y49
Quad_231:MGT_X1Y49: get_hw_sio_plls=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/COMMON_X1Y12/QPLL0
Quad_231:MGT_X1Y50: DESCRIPTION=Link 2
Quad_231:MGT_X1Y50: STATUS=NO LINK
Quad_231:MGT_X1Y50: QPLL0_STATUS=LOCKED
Quad_231:MGT_X1Y50: LINE_RATE=28.090
Quad_231:MGT_X1Y50: LOGIC.ERRBIT_COUNT=0007A8450BE4
Quad_231:MGT_X1Y50: RX_RECEIVED_BIT_COUNT=64349472000
Quad_231:MGT_X1Y50: TX_PATTERN=PRBS 31-bit
Quad_231:MGT_X1Y50: RX_PATTERN=PRBS 31-bit
Quad_231:MGT_X1Y50: LOOPBACK=None
Quad_231:MGT_X1Y50: TX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y50/TX
Quad_231:MGT_X1Y50: RX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y50/RX
Quad_231:MGT_X1Y50: NAME=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y50
Quad_231:MGT_X1Y50: get_hw_sio_plls=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/COMMON_X1Y12/QPLL0
Quad_231:MGT_X1Y51: DESCRIPTION=Link 3
Quad_231:MGT_X1Y51: STATUS=NO LINK
Quad_231:MGT_X1Y51: QPLL0_STATUS=LOCKED
Quad_231:MGT_X1Y51: LINE_RATE=28.102
Quad_231:MGT_X1Y51: LOGIC.ERRBIT_COUNT=00079BF75C40
Quad_231:MGT_X1Y51: RX_RECEIVED_BIT_COUNT=65079381280
Quad_231:MGT_X1Y51: TX_PATTERN=PRBS 31-bit
Quad_231:MGT_X1Y51: RX_PATTERN=PRBS 31-bit
Quad_231:MGT_X1Y51: LOOPBACK=None
Quad_231:MGT_X1Y51: TX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y51/TX
Quad_231:MGT_X1Y51: RX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y51/RX
Quad_231:MGT_X1Y51: NAME=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/MGT_X1Y51
Quad_231:MGT_X1Y51: get_hw_sio_plls=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_231/COMMON_X1Y12/QPLL0
# close_hw_target [current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]]
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
close_hw_target: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 611.055 ; gain = 0.000
# disconnect_hw_server localhost:3121
# close_hw
****** Webtalk v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-6284-sc-cs-371166/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] 'D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-6284-sc-cs-371166/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Fri May 5 11:56:55 2017. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.1/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Fri May 5 11:56:55 2017...
INFO: [Common 17-206] Exiting Vivado at Fri May 5 11:56:55 2017...
step finished

Error: Could not find regular expression in step 2 of test 5 - "(.*)Quad_231:MGT_X1Y48:\s+STATUS=2\d\.\d\d\d Gbps"

Error: Could not find regular expression in step 2 of test 5 - "(.*)Quad_231:MGT_X1Y48:\s+LOGIC.ERRBIT_COUNT=000000000000"

Error: Could not find regular expression in step 2 of test 5 - "(.*)Quad_231:MGT_X1Y49:\s+STATUS=2\d\.\d\d\d Gbps"

Error: Could not find regular expression in step 2 of test 5 - "(.*)Quad_231:MGT_X1Y49:\s+LOGIC.ERRBIT_COUNT=000000000000"

Error: Could not find regular expression in step 2 of test 5 - "(.*)Quad_231:MGT_X1Y50:\s+STATUS=2\d\.\d\d\d Gbps"

Error: Could not find regular expression in step 2 of test 5 - "(.*)Quad_231:MGT_X1Y50:\s+LOGIC.ERRBIT_COUNT=000000000000"

Error: Could not find regular expression in step 2 of test 5 - "(.*)Quad_231:MGT_X1Y51:\s+STATUS=2\d\.\d\d\d Gbps"

Error: Could not find regular expression in step 2 of test 5 - "(.*)Quad_231:MGT_X1Y51:\s+LOGIC.ERRBIT_COUNT=000000000000"

Info: Result for step 0: Pass
Info: Result for step 1: Pass
Info: Result for step 2: Fail

Info: The test took 0 hours, 03 minutes, and 57 seconds. 0:03:57

 

 

 

 

 

And the IBERT FIREFLY test fails with:

 

Info: IBERT FIREFLY test started...

Info: The test will take 0 hours, 03 minutes, and 48 seconds. 0:03:48

Info: This step started at: 2017-05-05 11:58:45

****** Vivado v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source {tcl\vcu118_ibert_bank_firefly.tcl}
# open_hw
# connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2017.1
**** Build date : Apr 14 2017-19:11:07
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

 


# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
# set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
# open_hw_target -jtag_mode 1
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
INFO: [Labtoolstcl 44-467] Setting hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331 into jtag_mode
# scan_ir_hw_jtag 6 -tdi 0b
# scan_ir_hw_jtag 6 -tdi 3f
# close_hw_target
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# set_property PROGRAM.FILE {[pwd]/../bitstream/ibert_bank_all.bit} [lindex [get_hw_devices] 0]
# current_hw_device [lindex [get_hw_devices] 0]
# refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0]
INFO: [Labtools 27-1435] Device xcvu9p (JTAG device index = 0) is not programmed (DONE status = 0).
# program_hw_devices [lindex [get_hw_devices] 0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:46 ; elapsed = 00:00:46 . Memory (MB): peak = 409.754 ; gain = 2.098
# close_hw_target [current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]]
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# disconnect_hw_server
# close_hw
****** Webtalk v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-6476-sc-cs-371166/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] 'D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-6476-sc-cs-371166/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Fri May 5 11:59:45 2017. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.1/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Fri May 5 11:59:45 2017...
INFO: [Common 17-206] Exiting Vivado at Fri May 5 11:59:45 2017...
step finished

Info: This step started at: 2017-05-05 11:59:45

****** Vivado v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source {tcl\vivado_ibert_reset.tcl}
# open_hw
# catch {disconnect_hw_server localhost:3121}
# connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
# set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# current_hw_device [lindex [get_hw_devices xcvu9p_0] 0]
# refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcvu9p_0] 0]
INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 IBERT core(s).
# set_property PORT.QPLL0RESET 1 [get_hw_sio_commons *];
# commit_hw_sio [list [get_hw_sio_commons {*}] ]
# set_property PORT.QPLL0RESET 0 [get_hw_sio_commons *];
# commit_hw_sio [list [get_hw_sio_commons {*}] ]
# set_property PORT.QPLL1RESET 1 [get_hw_sio_commons *];
# commit_hw_sio [list [get_hw_sio_commons {*}] ]
# set_property PORT.QPLL1RESET 0 [get_hw_sio_commons *];
# commit_hw_sio [list [get_hw_sio_commons {*}] ]
# set_property PORT.CPLLRESET 1 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# set_property PORT.CPLLRESET 0 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# set_property PORT.GTRXRESET 1 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# set_property PORT.GTRXRESET 0 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# set_property PORT.GTTXRESET 1 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# set_property PORT.GTTXRESET 0 [get_hw_sio_gts *];
# commit_hw_sio [list [get_hw_sio_gts {*}] ]
# refresh_hw_sio [get_hw_sio_gts *]
# refresh_hw_sio [get_hw_sio_commons *]
# close_hw_target [current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]]
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
close_hw_target: Time (s): cpu = 00:00:00 ; elapsed = 00:00:10 . Memory (MB): peak = 610.969 ; gain = 0.000
# disconnect_hw_server localhost:3121
# close_hw
****** Webtalk v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-9956-sc-cs-371166/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] 'D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-9956-sc-cs-371166/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Fri May 5 12:00:14 2017. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.1/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Fri May 5 12:00:14 2017...
INFO: [Common 17-206] Exiting Vivado at Fri May 5 12:00:14 2017...
step finished

Info: This step started at: 2017-05-05 12:00:14

****** Vivado v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source {tcl\vcu118_ibert_bank_firefly_status.tcl}
# open_hw
# catch {disconnect_hw_server localhost:3121}
# connect_hw_server -url localhost:3121
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
# current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
# set_property PARAM.FREQUENCY 15000000 [get_hw_targets */xilinx_tcf/Digilent/*]
# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
# current_hw_device [lindex [get_hw_devices xcvu9p_0] 0]
# refresh_hw_device [lindex [get_hw_devices xcvu9p_0] 0]
INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 IBERT core(s).
refresh_hw_device: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 603.047 ; gain = 327.684
# set xil_newLinks [list]
# set xil_newLink [create_hw_sio_link -description {Link 0} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y56/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y56/RX] 0] ]
# lappend xil_newLinks $xil_newLink
# set xil_newLink [create_hw_sio_link -description {Link 1} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y57/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y57/RX] 0] ]
# lappend xil_newLinks $xil_newLink
# set xil_newLink [create_hw_sio_link -description {Link 2} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y58/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y58/RX] 0] ]
# lappend xil_newLinks $xil_newLink
# set xil_newLink [create_hw_sio_link -description {Link 3} [lindex [get_hw_sio_txs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y59/TX] 0] [lindex [get_hw_sio_rxs localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y59/RX] 0] ]
# lappend xil_newLinks $xil_newLink
# set xil_newLinkGroup [create_hw_sio_linkgroup -description {Link Group 0} [get_hw_sio_links $xil_newLinks]]
# unset xil_newLinks
# set_property TX_PATTERN {PRBS 31-bit} [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property RX_PATTERN {PRBS 31-bit} [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property TXPRE {2.21 dB (01001)} [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property TXPOST {6.02 dB (10100)} [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property TXDIFFSWING {254 mV (00010)} [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.TX_RESET_DATAPATH 1 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.TX_RESET_DATAPATH 0 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.RX_RESET_DATAPATH 1 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.RX_RESET_DATAPATH 0 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.MGT_ERRCNT_RESET_CTRL 1 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# set_property LOGIC.MGT_ERRCNT_RESET_CTRL 0 [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# commit_hw_sio [get_hw_sio_links -of_objects [get_hw_sio_linkgroups {LINKGROUP_0}]]
# refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xcvu9p_0] 0]
INFO: [Labtools 27-2302] Device xcvu9p (JTAG device index = 0) is programmed with a design that has 1 IBERT core(s).
# refresh_hw_sio [list [get_hw_sio_links {localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y56/TX->localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y56/RX}] ]
# refresh_hw_sio [list [get_hw_sio_links {localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y57/TX->localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y57/RX}] ]
# refresh_hw_sio [list [get_hw_sio_links {localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y58/TX->localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y58/RX}] ]
# refresh_hw_sio [list [get_hw_sio_links {localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y59/TX->localhost:3121/xilinx_tcf/Digilent/*/0_1_0_0/IBERT/Quad_233/MGT_X1Y59/RX}] ]
# puts "Waiting 120 seconds for test to run."
Waiting 120 seconds for test to run.
# after [expr 120 * 1000]
# set offset 48
# set initial_links 0
# for {set i $offset} {$i <= 51} {incr i} {
# set j [expr {$i - $offset + $initial_links}]
# set display_name [get_property {DISPLAY_NAME} [lindex [get_hw_sio_gts] $i]]
# set quad_name [lindex [split [get_property {NAME} [lindex [get_hw_sio_gts] $i]] /] 6]
# set qpll0 [expr [expr $i / 4] * 6]
# #set qpll1 [expr [expr [expr $i / 4] * 6] + 1]
# #set cpll0 [expr $qpll0 + 2 + [expr $i%4]]
# puts "$quad_name:$display_name: DESCRIPTION=[get_property {DESCRIPTION} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: STATUS=[get_property {STATUS} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: QPLL0_STATUS=[get_property {QPLL0_STATUS} [lindex [get_hw_sio_plls] $qpll0]]"
# #puts "$quad_name:$display_name: QPLL1_STATUS=[get_property {QPLL1_STATUS} [lindex [get_hw_sio_plls] $qpll1]]"
# #puts "$quad_name:$display_name: CPLL_STATUS=[get_property {PLL_STATUS} [lindex [get_hw_sio_plls] $cpll0]]"
# puts "$quad_name:$display_name: LINE_RATE=[get_property {LINE_RATE} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: LOGIC.ERRBIT_COUNT=[get_property {LOGIC.ERRBIT_COUNT} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: RX_RECEIVED_BIT_COUNT=[get_property {RX_RECEIVED_BIT_COUNT} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: TX_PATTERN=[get_property {TX_PATTERN} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: RX_PATTERN=[get_property {RX_PATTERN} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: LOOPBACK=[get_property {LOOPBACK} [lindex [get_hw_sio_links] $j]]"
# # Debug lines to insure the correct alignment of the get_hw_sio_gts, get_hw_sio_links, and get_hw_sio_plls numbering
# puts "$quad_name:$display_name: TX_ENDPOINT=[get_property {TX_ENDPOINT} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: RX_ENDPOINT=[get_property {RX_ENDPOINT} [lindex [get_hw_sio_links] $j]]"
# puts "$quad_name:$display_name: NAME=[get_property {NAME} [lindex [get_hw_sio_gts] $i]]"
# puts "$quad_name:$display_name: get_hw_sio_plls=[lindex [get_hw_sio_plls] $qpll0]"
# #puts "$quad_name:$display_name: get_hw_sio_plls=[lindex [get_hw_sio_plls] $qpll1]"
# #puts "$quad_name:$display_name: get_hw_sio_plls=[lindex [get_hw_sio_plls] $cpll0]"
# }
Quad_233:MGT_X1Y56: DESCRIPTION=Link 0
Quad_233:MGT_X1Y56: STATUS=28.125 Gbps
Quad_233:MGT_X1Y56: QPLL0_STATUS=LOCKED
Quad_233:MGT_X1Y56: LINE_RATE=28.125
Quad_233:MGT_X1Y56: LOGIC.ERRBIT_COUNT=00002C3B31CE
Quad_233:MGT_X1Y56: RX_RECEIVED_BIT_COUNT=62231479280
Quad_233:MGT_X1Y56: TX_PATTERN=PRBS 31-bit
Quad_233:MGT_X1Y56: RX_PATTERN=PRBS 31-bit
Quad_233:MGT_X1Y56: LOOPBACK=None
Quad_233:MGT_X1Y56: TX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y56/TX
Quad_233:MGT_X1Y56: RX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y56/RX
Quad_233:MGT_X1Y56: NAME=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y56
Quad_233:MGT_X1Y56: get_hw_sio_plls=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/COMMON_X1Y14/QPLL0
Quad_233:MGT_X1Y57: DESCRIPTION=Link 1
Quad_233:MGT_X1Y57: STATUS=NO LINK
Quad_233:MGT_X1Y57: QPLL0_STATUS=LOCKED
Quad_233:MGT_X1Y57: LINE_RATE=28.157
Quad_233:MGT_X1Y57: LOGIC.ERRBIT_COUNT=0003076B81D9
Quad_233:MGT_X1Y57: RX_RECEIVED_BIT_COUNT=63132899840
Quad_233:MGT_X1Y57: TX_PATTERN=PRBS 31-bit
Quad_233:MGT_X1Y57: RX_PATTERN=PRBS 31-bit
Quad_233:MGT_X1Y57: LOOPBACK=None
Quad_233:MGT_X1Y57: TX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y57/TX
Quad_233:MGT_X1Y57: RX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y57/RX
Quad_233:MGT_X1Y57: NAME=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y57
Quad_233:MGT_X1Y57: get_hw_sio_plls=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/COMMON_X1Y14/QPLL0
Quad_233:MGT_X1Y58: DESCRIPTION=Link 2
Quad_233:MGT_X1Y58: STATUS=NO LINK
Quad_233:MGT_X1Y58: QPLL0_STATUS=LOCKED
Quad_233:MGT_X1Y58: LINE_RATE=28.249
Quad_233:MGT_X1Y58: LOGIC.ERRBIT_COUNT=0002694653ED
Quad_233:MGT_X1Y58: RX_RECEIVED_BIT_COUNT=63924444240
Quad_233:MGT_X1Y58: TX_PATTERN=PRBS 31-bit
Quad_233:MGT_X1Y58: RX_PATTERN=PRBS 31-bit
Quad_233:MGT_X1Y58: LOOPBACK=None
Quad_233:MGT_X1Y58: TX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y58/TX
Quad_233:MGT_X1Y58: RX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y58/RX
Quad_233:MGT_X1Y58: NAME=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y58
Quad_233:MGT_X1Y58: get_hw_sio_plls=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/COMMON_X1Y14/QPLL0
Quad_233:MGT_X1Y59: DESCRIPTION=Link 3
Quad_233:MGT_X1Y59: STATUS=NO LINK
Quad_233:MGT_X1Y59: QPLL0_STATUS=LOCKED
Quad_233:MGT_X1Y59: LINE_RATE=28.125
Quad_233:MGT_X1Y59: LOGIC.ERRBIT_COUNT=0003E8B1C4D9
Quad_233:MGT_X1Y59: RX_RECEIVED_BIT_COUNT=64834154480
Quad_233:MGT_X1Y59: TX_PATTERN=PRBS 31-bit
Quad_233:MGT_X1Y59: RX_PATTERN=PRBS 31-bit
Quad_233:MGT_X1Y59: LOOPBACK=None
Quad_233:MGT_X1Y59: TX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y59/TX
Quad_233:MGT_X1Y59: RX_ENDPOINT=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y59/RX
Quad_233:MGT_X1Y59: NAME=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/MGT_X1Y59
Quad_233:MGT_X1Y59: get_hw_sio_plls=localhost:3121/xilinx_tcf/Digilent/210308A1D331/0_1_0_0/IBERT/Quad_233/COMMON_X1Y14/QPLL0
# close_hw_target [current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]]
INFO: [Labtoolstcl 44-464] Closing hw_target localhost:3121/xilinx_tcf/Digilent/210308A1D331
close_hw_target: Time (s): cpu = 00:00:00 ; elapsed = 00:00:10 . Memory (MB): peak = 611.230 ; gain = 0.000
# disconnect_hw_server localhost:3121
# close_hw
****** Webtalk v2017.1 (64-bit)
**** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
**** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-4160-sc-cs-371166/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] 'D:/software/rdf0387-vcu118-bit-es1-2016-4/vcu118_bit/tests/VCU118/.Xil/Vivado-4160-sc-cs-371166/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Fri May 5 12:02:42 2017. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2017.1/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Fri May 5 12:02:42 2017...
INFO: [Common 17-206] Exiting Vivado at Fri May 5 12:02:42 2017...
step finished

Error: Could not find regular expression in step 2 of test 7 - "(.*)Quad_233:MGT_X1Y56:\s+LOGIC.ERRBIT_COUNT=000000000000"

Error: Could not find regular expression in step 2 of test 7 - "(.*)Quad_233:MGT_X1Y57:\s+STATUS=2\d\.\d\d\d Gbps"

Error: Could not find regular expression in step 2 of test 7 - "(.*)Quad_233:MGT_X1Y57:\s+LOGIC.ERRBIT_COUNT=000000000000"

Error: Could not find regular expression in step 2 of test 7 - "(.*)Quad_233:MGT_X1Y58:\s+STATUS=2\d\.\d\d\d Gbps"

Error: Could not find regular expression in step 2 of test 7 - "(.*)Quad_233:MGT_X1Y58:\s+LOGIC.ERRBIT_COUNT=000000000000"

Error: Could not find regular expression in step 2 of test 7 - "(.*)Quad_233:MGT_X1Y59:\s+STATUS=2\d\.\d\d\d Gbps"

Error: Could not find regular expression in step 2 of test 7 - "(.*)Quad_233:MGT_X1Y59:\s+LOGIC.ERRBIT_COUNT=000000000000"

Info: Result for step 0: Pass
Info: Result for step 1: Pass
Info: Result for step 2: Fail

Info: The test took 0 hours, 03 minutes, and 56 seconds. 0:03:56

 

 

 

 

 

 

 

The rest of the tests passed.  Could anyone help me to pass these three tests?

 

Thanks!

 

 

 

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