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Visitor 7081
Visitor
2,737 Views
Registered: ‎02-25-2008

VHDL 2008

Support for VHDL-2008 in Vivado Synthesis is tentatively expected in the 2014.x release. Support for VHDL-2008 in simulation is expected in 2014.3.

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4 Replies
Xilinx Employee
Xilinx Employee
2,736 Views
Registered: ‎08-01-2008

Re: VHDL 2008

Support for VHDL-2008 in Vivado Synthesis is tentatively expected in the 2014.x release. Support for VHDL-2008 in simulation is expected in 2014.3.

Thanks and Regards
Balkrishan
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Explorer
Explorer
1,616 Views
Registered: ‎12-31-2012

Re: VHDL 2008

Was is the current status for support of VHDL 2008 in simulation? It seems it is still not there as of Vivado 15.2

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Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu
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Xilinx Employee
Xilinx Employee
1,603 Views
Registered: ‎02-14-2014

Re: VHDL 2008

Hello @rlewis65,

 

http://www.xilinx.com/support/answers/62678.html

Regards,
Ashish
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Observer reichardt
Observer
1,151 Views
Registered: ‎10-15-2008

Re: VHDL 2008

I just tried VHDL 2008 in Vivado 2015.4 and made the following observations:

 

1. The Vivado simulator does not yet support the fixed-point package with datatypes sfixed() and ufixed(). The reading of table E-1 in UG 900 p. 194 seems to be misleading.

 

2. Vivado synthesis supports those data types but it seems that the VHDL 2008 standard was implemented in a wrong way:

The IEEE VHDL LRM states in rule G 4.3:

"The data widths in the fixed-point package are designed so that there is no possibility of an overflow. This is a departure from the NUMERIC_STD model, which simply throws away underflow and overflow bits."

This implies for the add operator that an additional output bit has to be added (see table G.2) of the LRM.

 

But when I implemented the following code

 

library ieee;
use ieee.fixed_pkg.all;

entity FIXED_PACK is
port(A,B : in sfixed(3 downto -3);
     SUM : out sfixed(4 downto -3)
    );
end FIXED_PACK;
architecture ARCH of FIXED_PACK is
begin
  SUM <= A + B;
end ARCH;

 

i get the following error:

  • [Synth 8-690] width mismatch in assignment; target has 8 bits, source has 7 bits ["../VHDL_2008/VHDL_Codes/fixed_pack.vhd":11]

Could you confirm that this is an error and could you please give as a roadmap which explains the complete implementation of the VHDL 2008 standard for simulation and synthesis which was finally defined already 7 years ago.

 

with kind regards

Juergen

 

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