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bloodstalker
Visitor
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5,760 Views
Registered: ‎03-06-2013

VHDL code for a schmetacis

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hello,

i have made a schmetatic in ise design suite but to use isim i need the vhdl code.ise itself turns the schmatic into vhdl for certain processes.how can i get that code? or is there an option in ise that gives me the vhdl code for my schematic design to useit for isim?

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7,339 Views
Registered: ‎07-15-2008

How very mean spirited some people are :-) and such poor advice too.

 

The most experienced HDL engineers will have a schematic in their mind when they write HDL.

Ok it won’t be at gate level, unless they are doing something particularly challenging, then it may be :-)

 

Good HDL engineers have a foundation in hardware design, and many started out by drawing schematics, it is a great approach to take if you are learning about FPGA’s.. keep it up.

 

Anyway about the VHDL file you want, its auto generated all you need to do is find it, search your project directory for a file with the same name as your top level schematic.. the extension will be odd (maybe something like .vhf)..

 

Find it, copy it, change the extension to .vhd and you have your vhdl file.

Generate a new project and import your vhdl file..

 

search for *.V* and look for somthing with your file name

 

Have a good one,,, Bob

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8 Replies
rlewis65
Explorer
Explorer
5,748 Views
Registered: ‎12-31-2012

The answer is to specify your design using VHDL or Verilog instead of using schematic entry. In other words, do not use schematic entry. It's antiquated. No one uses it for serious design.

---------------------------------------------------------------------------------
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu
7,340 Views
Registered: ‎07-15-2008

How very mean spirited some people are :-) and such poor advice too.

 

The most experienced HDL engineers will have a schematic in their mind when they write HDL.

Ok it won’t be at gate level, unless they are doing something particularly challenging, then it may be :-)

 

Good HDL engineers have a foundation in hardware design, and many started out by drawing schematics, it is a great approach to take if you are learning about FPGA’s.. keep it up.

 

Anyway about the VHDL file you want, its auto generated all you need to do is find it, search your project directory for a file with the same name as your top level schematic.. the extension will be odd (maybe something like .vhf)..

 

Find it, copy it, change the extension to .vhd and you have your vhdl file.

Generate a new project and import your vhdl file..

 

search for *.V* and look for somthing with your file name

 

Have a good one,,, Bob

View solution in original post

rlewis65
Explorer
Explorer
5,730 Views
Registered: ‎12-31-2012

That's backward, it's like saying you have to learn Assembler before you can code in C++. Schematic entry was fine in 1992. It has no place in modern design.

---------------------------------------------------------------------------------
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu
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5,725 Views
Registered: ‎07-15-2008

No, it not like saying “you have to learn Assembler before you can code in C++.”

I didn’t say that you did.

 

I’m afraid its clear to me that you lack depth of understanding on this subject, yet you give your advice so confidently.

 

Bob

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rlewis65
Explorer
Explorer
5,719 Views
Registered: ‎12-31-2012
Hmmm. "It is like..." /= "You said". So I stated my opinion and without you knowing anything about me you launch a personal attack. How very mean spirited some people are and such poor advice too.
---------------------------------------------------------------------------------
I like these books:
Free Range VHDL (free), http://www.freerangefactory.org/site/pmwiki.php/Main/Books
VHDL for Logic Synthesis, Andrew Rushton
FPGA Prototyping by VHDL Examples, Pong P Chu
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mcgett
Xilinx Employee
Xilinx Employee
5,698 Views
Registered: ‎01-03-2008
bobster, in your first reply in this thread you said "drawing schematics is a great approach to take if you are learning abut FPGAs, keep it up". While this isn't an absolute statement promoting the need to learn schematic entry (assembly) before learning an HDL (c++) I think many readers would consider it pretty close.

I agree that all FPGA designers need to understand hardware boolean logic design and most people will learn this with boolean logic gate figures, but I don't agree with designers struggling through an antiquated and rapidly deprecating schematic entry design flow. The amount of time that it takes to become even moderately proficient in a schematic tool is better spent in leaning and becoming proficient in an HDL.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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syedz
Moderator
Moderator
5,696 Views
Registered: ‎01-16-2013

When you run ISIM the tool will itself generate .vhf file which will be used for simulation,

However If you want to generate vhdl file from schematic then you can use sch2vhdl command in command prompt of ISE.

type sch2vhdl -help to know more about this command

 

 

Thanks,

Syed

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gszakacs
Instructor
Instructor
5,688 Views
Registered: ‎08-14-2007

I don't really want to back any side of this sparring match, but as someone who has been designing

logic with schematics since before HDL's were around, I think that it does make sense to learn

the basics of logic design schematically before learning to "code" in an HDL.  In fact, I like a

graphical representation of a design (not at a gate level) even when using HDL for the "guts" of

the logic.  Unfortunately, Xilinx does not provide usable schematic entry tools (in my opinion)

and hasn't since they dropped the Aldec front end (since Foundation version 4.1i).  So I have

been dragged grudgingly into using HDL for the top level as well as the guts of my designs.

 

My comment is that schematics have their place in logic design - including FPGA's, but that the

ISE schematics have no place in any serious design.  I may be a dying breed, since I also

do board level design - and that is done with schematics by most people still.  When I started

with Xilinx Alliance tools, I used the same schematic entry (ViewDraw) for both board level and

FPGA logic design.

 

It seems strange to me that so many people who have never tried hierarchical schematic

design and have no idea how it can be properly used will come out and say that text entry

is better.  I never used gate level schematic entry to create state machines - that was done

in HDL.  But with a decent design package, I could write my HDL and end up with a

schematic symbol or "macro" to drop into the overall design.  The schematic level made the

data flow much clearer than you could with a pile of text instantiations.

 

In a world where everything else is going away from text and towards graphical user interface

it really seems strange that hardware design is moving the other way.

 

OK - I've sad my $.02 worth - carry on!

 

-- Gabor

-- Gabor
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