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hupaa
Explorer
Explorer
3,016 Views
Registered: ‎04-29-2014

VHDL statemachine

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Hello,

I' ve a question about signal assignment in a case in vhdl.

In my code, there is a signal called "CONTROL"

 

signal CONTROL : std_logic := '0';

 

I've a statemachine with 10 states. in state 2 I have this assignment (CONTROL <= '1';).

and in state 9 again I have this assignment (CONTROL <= '0')

 

and there is no change on this signal between these two states.

In simulation every thing is OK. CONTROL signal in state2  will be '1' and  stay '1' until state 9. and then will be '0'. But in chipscope CONTROL signal can stay '1' just for one clock sycle! It means in state 3 it has the '0' value while I didn't write any change on this signal up to state 9!

Could you please guide me

Thanks.

 

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anshpmrl
Adventurer
Adventurer
3,833 Views
Registered: ‎04-07-2014

Hi Hupaa,

 

  1. Does the signal assignment CONTROL <= '0' in state machine  combinational or registerd ?
  2. If it is combinational, you need to assign values to CONTROL  in all 10  states.Unless it will infer a latch,which is not a good coding practise(may introduce glitches in hardware).
  3. If it is registered ,it maynot create any problem in implementation(which infer FFs).
  4. Also it would be better if you add when others => clause and necessary signal assignments under the same to bring back the state machine from unpredictable states.

Thanks,

Akshay

 

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4 Replies
yashp
Moderator
Moderator
2,996 Views
Registered: ‎01-16-2013
Hello,

When you mentioned simulation is this Behavioral simulation?
If yes, Please check post-synthesis and post-implementation simulation results.

Then you will see where is the difference occurs during synthesis or implementation.

Thanks,
Yash
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anshpmrl
Adventurer
Adventurer
3,834 Views
Registered: ‎04-07-2014

Hi Hupaa,

 

  1. Does the signal assignment CONTROL <= '0' in state machine  combinational or registerd ?
  2. If it is combinational, you need to assign values to CONTROL  in all 10  states.Unless it will infer a latch,which is not a good coding practise(may introduce glitches in hardware).
  3. If it is registered ,it maynot create any problem in implementation(which infer FFs).
  4. Also it would be better if you add when others => clause and necessary signal assignments under the same to bring back the state machine from unpredictable states.

Thanks,

Akshay

 

View solution in original post

anusheel
Moderator
Moderator
2,982 Views
Registered: ‎07-21-2014

Hello,

 

To debug this problem you should use respective simulation options.

 

There are possibilities that your design passes in one simulation and fails in later stage.

 

Compare the differences between the results and find out the root cause then correct your design accordingly.

 

In case you need more help, upload your design file or test case.

 

Thanks,

Anusheel

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hupaa
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Registered: ‎04-29-2014

Hello,

Thank you very much for your guidance.

 

 

Regards

 

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