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kaiyangsun
Visitor
Visitor
4,240 Views
Registered: ‎10-26-2015

Verilog for fpga Spartan 6 bus interface to QUICC MC68360 MCU

We try to use verilog to write the fpga data interface to QUICC MC68360 MCU, but complete system crash just after FPGA is loaded and started.

This verilog code is to write(low enable) and read(high enable) data from 1 bit adress (addr 0 and addr 1) inside fpga. Looks like the data bus not work properly.

 

 

 


`timescale 1ns / 1ps module test_NEW_SPART( clock, CSL, addr, data, RD_WRL ); parameter DATA_WIDTH = 8; input clock; input CSL; input RD_WRL; input addr; // 1 bit addr inout [DATA_WIDTH-1:0] data; //-------------------// reg [DATA_WIDTH-1:0] data_out; reg [DATA_WIDTH-1:0] temp_data [1:0]; //---------- assign data = (!CSL && RD_WRL) ? data_out : 8'bz; initial begin temp_data[0] <= 8'h05; temp_data[1] <= 8'h07; end always @ (posedge clock) begin: MP_TEST_WR if (!CSL && !RD_WRL) begin temp_data[addr] <= data; end end always @ (posedge clock) begin: MP_TEST_RD if (!CSL && RD_WRL ) begin data_out <= temp_data[addr]; end end endmodule

 

 

 

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gszakacs
Professor
Professor
4,220 Views
Registered: ‎08-14-2007

Did you check that all of your pins are properly constrained and match the actual hardware schematic?  In the place & route report you should see 100% LOCed IOBs.  Example:

 

IO Utilization:
  Number of bonded IOBs:                       346 out of     400   86%
    Number of LOCed IOBs:                      346 out of     346  100%

 

Where does your clock come from?  Is is synchronous to the bus?

 

You say there is a "complete system crash".  What does that mean?  Are there other devices on this bus, or just the FPGA and MCU?

-- Gabor
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kaiyangsun
Visitor
Visitor
4,213 Views
Registered: ‎10-26-2015

Thank you!

Here is the information:

 

IO Utilization:
  Number of bonded IOBs:                        12 out of     102   11%
    Number of LOCed IOBs:                       11 out of      12   91%

 

The Clock comes from MCU.

 

on the data bus, we have MCU, FPGA, DRAM. After MCU initialize the FPGA, The whole system freeze. We lose communication with MCU.

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kaiyangsun
Visitor
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Registered: ‎10-26-2015

Sorry, Gabor.

 

I did not assign the CSL pin..

 

this is the updated information:

 


IO Utilization:
  Number of bonded IOBs:                        12 out of     102   11%
    Number of LOCed IOBs:                       12 out of      12  100%

 

But stil....the system not work.

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gszakacs
Professor
Professor
4,201 Views
Registered: ‎08-14-2007

OK.  This CSL pin - is it a decoded chip-select address range just for the FPGA?  If not, I could see that the FPGA would interfere with other bus read operations.

-- Gabor
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kaiyangsun
Visitor
Visitor
4,192 Views
Registered: ‎10-26-2015

Hi, Gabor. Yes, now the FPGA interferes with other bus read operations. CSL, this chip selsect pin is only for FPGA. Now we do the test, only send CSL signal to FPGA from MCU, and remove all other pin connection. This time, we could talk with MCU from PC, while FPGA still not work, no communication between FPGA and MCU.

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gszakacs
Professor
Professor
4,187 Views
Registered: ‎08-14-2007

I would think that rather than disconnecting pins, you should be able to just prevent the FPGA from driving the data bus by commenting out the following line:

 

assign data = (!CSL && RD_WRL) ? data_out : 8'bz;

 

If that prevents the system lock-up, then I would suggest looking at the CSL signal to make sure it really only asserts low when the FPGA is being accessed and not while other bus operations are going on.

-- Gabor
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