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201211047
Visitor
Visitor
1,259 Views
Registered: ‎01-01-2015

Video Timing Controller IP Configuration

I have configured the Video Timing Controller IP with the following settings:

 

1) Video Format : 576i

2) Active Video: Polarity High

3) Vsync/Hsync: Polarity Low

4) Enabled Detection and Generation

5) Interlaced Video Support

6) Not used the AXI interface

7) Active Low Reset

8) 27 MHz clock input(also tried with 13.5MHz)

9) Permanently enabled 'clken', 'det_en','gen_en'

 

I am not quite clear with the appropriate values for Frame Sync horizontal and vertical positions(Presently, I am using the default value '0' for both vertical and horizontal positions of frame sync). I am using video input signals corresponding to PAL-B (4:2:2 format). 

 

The output signals 'vsync' and 'hsync' from the IP do not show any changes and remain at '0' permanently despite observing it for a pretty long time in the waveform viewer(after configuring the bitstream in a Kintex 7 device). What could be the possible mistakes that I am making?

 

 

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bwiec
Xilinx Employee
Xilinx Employee
1,201 Views
Registered: ‎08-02-2011

Can you post a screenshot showing your configuration of the core and also how you connected it (i.e. clocks, resets, bus connections, etc)?

Are you using the AXI Lite interface or constant mode?
www.xilinx.com
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