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asrarhashmitud
Observer
Observer
4,442 Views
Registered: ‎07-23-2014

Vivado 2014.3 failing to place design

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Hello All,

 

I recently migrated my design from 2014.2 to 2014.3. It was synthesizing and implementing easily on 2014.2 but after upgrading to 2014.3 I cannot implement it anymore. It gives a strange error about being unable to place IOs due to unavailbility of sites!! Although only 32% of top level IO are assigned.

 

[Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0).
The following Groups of I/O terminals have not sufficient capacity:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: In RangeId: 1 has only 0 sites available on device, but needs 1 sites.
Term: resetn

 

This message never came on 2014.2

 

There is a whole lota space free to place IOs but it is still failing. Can anyone help me out with this?

 

Best Regrds

Asrar

io.png
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vsrunga
Xilinx Employee
Xilinx Employee
6,075 Views
Registered: ‎07-11-2011

Hi,

 

Please check if the tool is trying to connect resetn to top level ports may be drivers to it are optimized for some reasons?

and connect it appropriately, refer this link on related discussion

http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Can-t-implement-design-in-Vivado-2013-4-Place-30-58/td-p/489890

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pulim
Xilinx Employee
Xilinx Employee
4,434 Views
Registered: ‎02-16-2014
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vsrunga
Xilinx Employee
Xilinx Employee
6,076 Views
Registered: ‎07-11-2011

Hi,

 

Please check if the tool is trying to connect resetn to top level ports may be drivers to it are optimized for some reasons?

and connect it appropriately, refer this link on related discussion

http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Can-t-implement-design-in-Vivado-2013-4-Place-30-58/td-p/489890

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asrarhashmitud
Observer
Observer
4,417 Views
Registered: ‎07-23-2014

Hi,

 

I did try this link already. It asks to manually remove the unused ports from the design. But the fact is that there are no unused ports on the design and the ports that it gives error about are necessary to my design and they are very well within the number of available of allowed IO's.

 

Should I send you the entire project if you want me to so that may be you can have a better look at it.

 

 

Best Regards

Asrar

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vsrunga
Xilinx Employee
Xilinx Employee
4,415 Views
Registered: ‎07-11-2011

HI,

 

If possible please upload your deisgn here else will send you EZMOVE link

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asrarhashmitud
Observer
Observer
4,381 Views
Registered: ‎07-23-2014

Hello,

 

Thanks  for the link you provided.

 

I was trying the link that you sent me for looking into the top level wrapper that is generated.

 

and there I found the problem. It was in the ports. So earlier when I generated the top level wrapper it made "resetn" a "std_logic_vector (0 downto 0)" and consequently I added entry for that accordingly in my xdc file for pin assignment.

 

Afterwards I (during endless iterations) once deleted and re generated the wrapper and this time it made "resetn" a "std_logic"

"OUT OF ITS OWN WILL" :O and thats what was perhaps screwing the placer. From xdc it was looking for a port and from the top level it was getting a pin.

 

Anyways I updated the xdc file entries to [get_ports resetn] instead of [get_ports {resetn[0]}]

 

And the design finally works!! ....

 

I still don't know though why and how did it change it to std_logic instead of std_logic_vector(0 downto 0)???

and

why was this not coming up as an error in 2014.2???

 

If anyone from you is interested in answering or looking into this, they are most welcome and appreciated... Otherwise my problem is SOLVED :)

 

Thanks for the help everyone.

 

Best Regards

Asrar

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bbinb
Adventurer
Adventurer
2,022 Views
Registered: ‎07-09-2014

Hi,

 

I got this error when I had a typo in one of my port names in the constraint file. For example the name of the port was "dataIn" but I had written "data_In". Then Vivado 2013.2 gives this error.

 

bbinb

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