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naveenshankar
Contributor
Contributor
4,313 Views
Registered: ‎06-11-2014

Vivado ILA Error!!!!

Hi all,

 

     Vivado ILA Is giving me lots of trouble, I generated bit and Ltx file in vivado 14.1 version and using same version hardware manager i fused code into FPGA. But i get this following error!!!

 

ERROR: [Labtools 27-147] vcse_server: Multiple trigger marks in window: 0, buffer index: 4.
ERROR: [Labtools 27-147] vcse_server: Could not get Parameter: trace_data.
ERROR: [Labtools 27-1829] vcse_server failed during internal command 'CseXsdb_getParameters'. See previous error messages.

 

Even i have taken care of STA : Timing violations.

 

 Can any body help me with this problem...

 

Thank you in advance

Naveen S

 

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11 Replies
pulim
Xilinx Employee
Xilinx Employee
4,310 Views
Registered: ‎02-16-2014

Hi,

 

Can you reduce the JTAG clock frequency and see still yous ee teh same issue?

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ashishd
Xilinx Employee
Xilinx Employee
4,304 Views
Registered: ‎02-14-2014

Hello,

Please check the related threads
http://forums.xilinx.com/t5/Design-Tools-Others/Vivado-2014-1-Debug/td-p/458536
http://forums.xilinx.com/t5/Design-Tools-Others/what-happed-to-my-debugging/td-p/325781
Regards,
Ashish
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vijayak
Xilinx Employee
Xilinx Employee
4,293 Views
Registered: ‎10-24-2013

Hi @naveenshankar ,

 

I have seen few such cases where the design had timing violations and unconstrained paths.

Did you check that your design is fully constratined?

Thanks,Vijay
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pulim
Xilinx Employee
Xilinx Employee
4,270 Views
Registered: ‎02-16-2014

Naveen,

 

Just to add, the clock that is coming to debug hug is clean and free running.

If possible, please sahre the test case with me.

I will try to reproduce the issue at my end and will check if I could get any hint on the rootcause for the issue.

 

Thanks,

Manusha

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naveenshankar
Contributor
Contributor
4,256 Views
Registered: ‎06-11-2014

Hi Manusha,

 

             Ya Clk connected to ILA is clean and test cases you mean Exactly what??

 

Thank you

Naveen

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naveenshankar
Contributor
Contributor
4,255 Views
Registered: ‎06-11-2014

Hi Vijay,

 

    Yes my design is constrained and timing violations are taken care.. but still i am facing this problem

 

Thank you

Naveen

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achutha
Xilinx Employee
Xilinx Employee
4,240 Views
Registered: ‎07-01-2010

Can you check this in the latest version of Vivado 2014.4?

Regards,
Achutha
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naveenshankar
Contributor
Contributor
4,224 Views
Registered: ‎06-11-2014

Hi,

 

I keep getting this error, i dont understand the problem... can any body explain me the cause of this please??

 

ERROR: [Labtools 27-147] vcse_server: Arg. to function CseILA_unrollTraceMemory() failed:traceMemorySize >= (samplewordsizewithmark * sampleCnt * windowCnt)
ERROR: [Labtools 27-147] vcse_server: Could not get Parameter: trace_data.
ERROR: [Labtools 27-1829] vcse_server failed during internal command 'CseXsdb_getParameters'. See previous error messages.

 

Thank you

Naveen

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vijayak
Xilinx Employee
Xilinx Employee
4,016 Views
Registered: ‎10-24-2013

Hi Naveen,

Please check the unconstrained paths in your design. Run report timing summary..Refer to the screenshot.

Thanks,Vijay
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achutha
Xilinx Employee
Xilinx Employee
1,500 Views
Registered: ‎07-01-2010

Details of the Error:http://www.xilinx.com/support/answers/62421.html

Regards,
Achutha
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vijayak
Xilinx Employee
Xilinx Employee
1,487 Views
Registered: ‎10-24-2013

Hi @naveenshankar ,

Did that helped? let us know if you have any queries.

Thanks,Vijay
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