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Visitor
Visitor
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Registered: ‎09-10-2010

Vivado - LVDS output - constraint for _N pin only ?

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I wanted to know if the rules for Vivado IO constraints (XDC) apply equally to the pos (_P) and neg (_N) of an LVDS signal being driven out by the FPGA ?

 

Do I specify IO Location constraint for both _P and _N of this LVDS output ?

 

Also, I think drive strength cannot be changed for an LVDS output? Isn't this true?

 

Currently, am seeing LVDS output clock (from the FPGA) not toggling and so wanted to clarify these things.

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Teacher
Teacher
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Registered: ‎03-31-2012

@gauravbhatia Yes, you have to specify IO locations of both sides. No, the concept of drive strength doesn't apply to LVDS.

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Moderator
Moderator
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Registered: ‎07-01-2015

Hi @gauravbhatia,

 

Please go through https://www.xilinx.com/support/answers/53368.html 

https://www.xilinx.com/support/answers/57109.html

 

Which clock are you using? It should go through IBUFDS from the differential pins. Proper IO port constraining is needed according to the board you are using. 

Thanks,
Arpan
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Visitor
Visitor
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Registered: ‎09-10-2010

Thanks for the reply. Those links refer to an LVDS input.

 

I am driving an LVDS output clock from my FPGA to a DAC.

The internal signal goes through an ODDR and then an ODELAYE2 before it reaches an OBUFDS to create the differential (P & N) output.

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Scholar
Scholar
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Registered: ‎02-27-2008

g,

 

In a word:  yes.  The P and N outputs are treated identically, as they are in a LVDS capable IOB pair, so the delay difference between them is less than a few picoseconds (by design).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
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Registered: ‎10-14-2015

Hi @gauravbhatia,

 

For differential signalling only the P-side of the differential data port needs to be constrained in the input delay and output delay constraints,Delay between them very less.

 

The analysis of the N-side path is exactly the same as the P-side

 

Thanks,

Sarada

 

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Teacher
Teacher
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Registered: ‎03-31-2012

@gauravbhatia Yes, you have to specify IO locations of both sides. No, the concept of drive strength doesn't apply to LVDS.

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Visitor
Visitor
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Registered: ‎09-10-2010

Thanks. That is exactly what I wanted to know. That whether I should apply pin location constraints to both P and N of the differential output.

 

I did end up creating 2 builds.... one with pin location constraint defined for both P and N .... and the other with pin location constraint defined for N only. In both cases, Vivado didn't throw up any errors during implementation or bitstream generation. My original problem of being unable to get an output of this differential clock on these pins is still not resolved though.

 

Here are the constraints I am using for this differential clock signal:

 

set_property IOSTANDARD LVDS [get_ports {DAC_DATA_CLK_P}]
set_property IOSTANDARD LVDS [get_ports {DAC_DATA_CLK_N}]

set_property PACKAGE_PIN AB8 [get_ports {DAC_DATA_CLK_P}]          ......... removed this constraint in 2nd build
set_property PACKAGE_PIN AB7 [get_ports {DAC_DATA_CLK_N}]

set_property SLEW SLOW [get_ports {DAC_DATA_CLK_P}]
set_property SLEW SLOW [get_ports {DAC_DATA_CLK_N}]

 

I understand that the SLEW is not applicable to LVDS signal. So I plan on taking it out when I make the next build.

 

I measured the impedance on the board across the P and N traces going to the DAC and it measures to be 100 ohms.

 

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Moderator
Moderator
9,676 Views
Registered: ‎07-23-2015

What is the Bank VCCO voltage?

When you mean unable to get an output from these pins, you mean you don't see any activity on these lines? 

 

If there is activity, what exactly is the issue you facing. 

 

 

- Giri
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Teacher
Teacher
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Registered: ‎03-31-2012

@gauravbhatia how are you measuring the output? make sure you look at it differentially and also realize that you will see only 350 mV of change across the receive termination resistor. 

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Visitor
Visitor
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Registered: ‎09-10-2010

The bank VCCO is 1.8V.

I don't see any activity on these differential lines. Am using a differential probe to scope it.

 

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Moderator
Moderator
7,215 Views
Registered: ‎07-23-2015

@gauravbhatia Can you share you Board Schematic section which shows this interface?

 

Did you make sure the Clk signal is fine inside the fabric as in it is getting generated properly. Maybe if you can elaborate a bit more on how you are generating the clock signal internally , it would help. 

- Giri
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Teacher
Teacher
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Registered: ‎03-31-2012

@gauravbhatia which FPGA are you using? Make sure you can make an LVDS output on a 1.8V bank.

Also how are you driving the differential outputs? Can you show the netlist / RTL which shows which IO you instantiate in the FPGA ?

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Visitor
Visitor
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Registered: ‎09-10-2010

Yes, I had checked the clock output in Simulation and it looked fine.

 

The issue turned out to be that I was given the older schematic and hence couldn't find the clock when I probed it on the board.

 

Still, this post answered my original question as to whether we should give Pin Location Constraint for both _P and _N pins connecting to a different output or input.

 

Thanks for all the replies !!

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