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Adventurer
Adventurer
5,577 Views
Registered: ‎04-24-2015

Vivado Logic Analyzer Procedure

I have been using Vivado Logic Analyzer for months. and believe me it took so much time to properly see the debug singals on waveform.  I usually mark the debug signals on block design and then synthesize and generate bitstream . But sometimes i can see my clock on debug "FCLK" or sometimes "ProcessingSystemFCLK, using (Setup_debug on synthesized designs ) . Then also sometimes i can see proper transiitons of waveform on ILA , and sometimes i can see only one straight value there;  No transiitons whatsoever. Sometimes I get LUTRAM error and sometimes the bit stream generated successfully.


 It will be appreciated if one can tell me the proper sequence for debugging signals and whether first to program device using Vivado or using SDK. And also kindly clarify above points too.


 thanks so much


Regards


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Xilinx Employee
Xilinx Employee
5,575 Views
Registered: ‎04-16-2012

Hello @live4perfection

 

Check this tutorial: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug940-vivado-tutorial-embedded-design.pdf

 

It will help you.

 

Thanks,

Vinay

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Adventurer
Adventurer
5,565 Views
Registered: ‎04-24-2015

@vuppala thanks for this tutorial . But i had followed exact steps and there there is a sentence :

set clock domain as " zynq_design_1_i/processing_system7_0/inst/FCLK_CLK0"

This exact domain i cannot find in synthesized design !!

 

So this might be a problem. what should i do ? and sometimes it is usually shown in some projects and in some it wont. :/

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Adventurer
Adventurer
5,556 Views
Registered: ‎04-24-2015

No . Thanks It work. One signal is missing to capture it.

 

that clock domain is not  an issue :)

 THANKS AGAIN :)

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