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Observer
Posts: 29
Registered: ‎08-25-2015
Accepted Solution

(Vivado) block memory reset pin

Hi.

 

I'm a beginner for designing digital system on FPGAs.

 

I'm using kintex 7 family FPGA and design my system with verilog code on Vivado Design Suite.

 

I wanna use block memory and what I want is to reset all of data in block memory by 0 value.

 

When I open IP core of block memory, there is option for whether I would use rsta pin.

 

In datasheet of block memory, it says about rsta pin like below.

 

"Port A Set/Reset: Resets the Port A memory output latch or output
register. Optional in all configurations."

 

Does it means what I wanna do ? (reset all of data in block memory by 0 value)

 

Can I reset all of the data in block memory to 0 value by insert a pulse to rsta pin?


Accepted Solutions
Scholar
Posts: 2,101
Registered: ‎04-26-2015

Re: (Vivado) block memory reset pin

No, that will not do what you require. The only ways to clear a block RAM are (a) reconfigure the relevant section of the FPGA (ir. partial reconfiguration) or (b) step through each address and clear it to zero. The block RAM has no functionality for a single-cycle clear.

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All Replies
Scholar
Posts: 2,101
Registered: ‎04-26-2015

Re: (Vivado) block memory reset pin

No, that will not do what you require. The only ways to clear a block RAM are (a) reconfigure the relevant section of the FPGA (ir. partial reconfiguration) or (b) step through each address and clear it to zero. The block RAM has no functionality for a single-cycle clear.