05-12-2016 05:18 PM
On vivado, I ran synthesis, then ran implementation, then ran simulation.
While in simulation process, vivado is stuck at executing elaborate step.
I saw 2015.1 fixed this problem, but it is not working.
My version of vivado is 2015.4
Please help!! I attached my vhd file.
The vhd file is generated by HDL coder(HLS tool for matlab)
05-12-2016 06:08 PM
Is this the only file you are trying to simulate? If so, what do you expect to happen?
This code describes an algorithm in RTL (like) code. That means that if you provide it with some inputs, and some clock pulses, it will provide the result of the algorithm.
As is, there is no input provided, and no clock provided - therefore, this module will do nothing. In order to get it to do something, you need a testbench - a VHDL module that creates a clock and a valid reset, instantiates your module (the device under test - or DUT) and then starts providing input data to the module.
WIthout this, the simulation won't do anything - it will just sit there (or terminate right away - hard to say which). This wouldn't be "stuck at elaboration", but wouldn't do anything after elaboration is complete, so it could be hard to tell the difference between them.
05-12-2016 06:45 PM
Thank you so much for your reply.
What I want is the latency.
When I use Vivado HLS converting C to vhdl, it gives latency information at the end.
But Vivado doesnt. so I guess I need to run simulation to get latency.
Is this right? will the running simulation will give me latency info?
Also I attached my testbench file.
07-14-2016 05:18 AM
Vivado could stuck at "executing elaborate" stage if error occurs during elaboration.
If it happens, you can press "background" button, then go to the "Log" or "Tcl Console" tab of "Project Manager" window. In these tabs there will be detailed description of the error. After that you can interrupt stuck backgrounded process by pressing "cancel" button in the bottom rigth corner if the "Project Manager" window.