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Participant jacob.varghese
Participant
3,435 Views
Registered: ‎05-28-2015

Vivado takes more time for sythesize,implementation and write bitstream

Hi All,

 

Tool : Vivado 15.2

 

Vivado takes more time for synthesize,implementaion, and wrie bitstream in my PC.

Is there any possible reason for this?

 

Thanks and regards,

Benjelo

 

 

 

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3 Replies
Moderator
Moderator
3,428 Views
Registered: ‎01-16-2013

Re: Vivado takes more time for sythesize,implementation and write bitstream

@jacob.varghese,

 

MAke sure you have sufficient free memory on machine when running Vivado:

 

The below link is the FPGA memory recommendations using Vivado:

http://www.xilinx.com/design-tools/vivado/memory.htm

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Moderator
Moderator
3,424 Views
Registered: ‎06-24-2015

Re: Vivado takes more time for sythesize,implementation and write bitstream

Hi @jacob.varghese,

 

Which OS are you using?
Make sure you are using supported OS. Refer to this link page 9 for supported OS:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug973-vivado-release-notes-install-license.pdf

 

Try to close all other programs and check if it is taking same amount of time.

 

Is it looking for nodelocked or floating license? It might be taking time to search through many locations for license. Set the XILINXD_LICENSE_FILE  variable to the location where license is located.

 

Select "Clear Cache" from the "Manage Licenses" tab in Vivado License Manager.

 

Check if servers are working properly.

 

Try running with Flow_RuntimeOptimized synthesis setting in Vivado.

Capture.PNG

 

Let me know if this helps.

 

Thanks,
Nupur

Thanks,
Nupur
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Moderator
Moderator
3,033 Views
Registered: ‎01-16-2013

Re: Vivado takes more time for sythesize,implementation and write bitstream

@jacob.varghese,

 

Any update on this post? If it is Large design consisting of complex loops then high runtime are expected. 

As suggested you can try using RuntimeOptimized for implementation as well which will run less iterations to reduce the runtime but this comes at an expense of phys_opt_design disabled.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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