FPGA Editor can be used to manually modify and existing routed design (.ncd). The documentation is here:
http://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/fpga_editor/fpga_editor.htm
See Design Flows/Placing and Routing Critical Components
See Procedures/Adding and Deleting Components, Nets
After saving the NCD edits you would need to generate a new bit file
In addition,
You can also try using RPM instead of Hard macros. These are handled effectively.
There's quite a bit of RPM macro documentation in the Constraint User Guide:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf
RLOC is the basic building block that defines relative location of the elements. The RLOC'd elements will group by default within a hierarchy or you can use U_SET or HU_SET to define the grouping. RLOC_ORIGIN will lock the macro to a specific location. You can add BEL constraints if necessary to further control the packing within a slice.
XAPP416 is old but still contains relavent information about RPM macros:
http://www.xilinx.com/support/documentation/application_notes/xapp416.pdf
Hope this helps.
Regards
Sikta
