cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Observer
Observer
2,240 Views
Registered: ‎03-29-2016

Why more delay from cfg_interrupt_n to cfg_interrupt_rdy_n

Hello iam doing PCIe communication between Xilinx FPGA(with ML605 board) and PC.

Using BMD design as reference..

The waveforms u can see in diagram..

My doubt is When data is transferred from FPGA to PC , FPGA will generate an INTx interrupt by asserting cfg_interrupt_n and cfg_interrupt_assert_n and i will get an acknowledgement from core with signal cfg_interrupt_rdy_n .

 

One thing i have observed is nearly 16 clock cycles delay time is there from cfg_interrupt_n to cfg_interrupt_rdy_n, why this many clock cycles it is taking....

 

can anybody say what is happening in this time...

interrupt timing.PNG
0 Kudos
Reply
0 Replies