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Anonymous
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XADC Event MODE

HI

 

I am trying to test XADC event mode in KC705.

I am using the two auxilliary input channels only(no calibration, no voltage/temperature sensing).

I want the XADC to sample these two inputs only once...i.e when an external switch is pressed.

 

So I have selected

Event mode

Single pass sequence mode enabling those two channels of XADC only.

 

I am using the registered switch input for the first time and then the ADC busy signal as the CONVST

 

But what I am seeing in the simulation is the ADC BUSY is even high before applying the switch input.

 

Is it expected(provided calibration is disabled)

 

Attached here are my design and test-bench.

 

I am using viv 2015.3

 

Where am I possibly going wrong??

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Xilinx Employee
Xilinx Employee
5,462 Views
Registered: ‎09-05-2007

Re: XADC Event MODE

Please note that you really should ask questions in a relevant board of this forum and not in the ‘Welcome & Join’ area. That way you stand a better chance of having others read your question and provide you with answers. In this case the ‘7 Series FPGAs’ board would have been a good choice.

 

Anyway....

 

UG480 (v1.8) page 73 says that ‘A Low-to-High transition (rising edge) on CONVST or CONVSTCLK defines the exact sampling instant for the selected analog-input channel’. As such, you should either provide a Low-to-High transition on the CONVST input OR you could provide a Low-to-High transition on the CONVSTCLK input.

 

In your ‘ug480.vhd’ file you appear to be driving both inputs. My guess is that ‘pulse’ connected to CONVST is your intended ‘event’. The connection of ‘dclk_bufg’ to the CONVSTCLK input is almost certainly incorrect and this input should be connected to ‘0’. As it stands, you are triggering a conversion every clock cycle and that just isn’t possible.

Ken Chapman
Principal Engineer, Xilinx UK
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