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Visitor smvog555
Visitor
2,727 Views
Registered: ‎04-13-2017

XADC Wizard IP core registers in FPGA

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Hi all,

Where are the IP core registers in the FPGA design? I'm doing a simulation and want to issue a software reset using the software reset register but don't know how to access this register space.


Thanks,
Sam 

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Scholar austin
Scholar
5,171 Views
Registered: ‎02-27-2008

Re: XADC Wizard IP core registers in FPGA

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The only reset I see is in the verilog (or VHDL),


The only registers I see are also in the verilog (or VHDL) generated by the wizard.

 

See page 83 of ug480

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar austin
Scholar
2,717 Views
Registered: ‎02-27-2008

Re: XADC Wizard IP core registers in FPGA

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The XADC block is instatiated into your design,

 

In verilog or VHDL.  If you look at the code, you will find a net for reset (basically it is a wire).  If you put a '1' on that signal, the XADC resets (and will remain in reset until that wire goes back to a '0').  All the registers are also in the code.  If you connect those registers to something, they may be read or written if your design needs to do that.  If you do not use the register, the wires get trimmed (removed).  Only what is used is placed and routed (connected up).

 

It is hardware:  it is not a microcontroller.  Verilog or VHDL is not a program.  The code describes the connections to be made in the hardware.  If you connect the rest to a reset button, it will reset when the button is pushed.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Participant fhknapp44
Participant
2,709 Views
Registered: ‎02-25-2015

Re: XADC Wizard IP core registers in FPGA

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Austin: I use schematic entry, not VHDL/VERLOG. Well, not exactly true, I have a BCD to 7 segment display piece of VHDL as it is just a state machine. You are saying that I have to over ride this XADC. Where/how do I add this VHLD code?

Floyd Knapp

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Visitor smvog555
Visitor
2,692 Views
Registered: ‎04-13-2017

Re: XADC Wizard IP core registers in FPGA

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Thanks Austin,

 

So I can infer from your response that the software reset referenced on pg 17 at the beginning of table 2-4 of the XADC wizard v3.0 data sheet is the same signal that's connected to the top level reset port of the core?

I could not find the registers referenced in the table in the example design. Are they the same registers as the INIT_40 through INIT_5F or are they physically located somewhere else?

 

-Sam

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Scholar austin
Scholar
5,172 Views
Registered: ‎02-27-2008

Re: XADC Wizard IP core registers in FPGA

Jump to solution

The only reset I see is in the verilog (or VHDL),


The only registers I see are also in the verilog (or VHDL) generated by the wizard.

 

See page 83 of ug480

Austin Lesea
Principal Engineer
Xilinx San Jose
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