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Visitor
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5,797 Views
Registered: ‎09-09-2015

Xilinx Display Port v6.1 - Rx with dp159 retimer.

Hi,all!

I try to run display port core with ti sn65dp159 retimer.

but link-tranining of source(GPU) - dp159 - sink(7 series fpga) is failed.

The displayport cable is connected between source(GPU) and adapter(sink).the initial value of LINK_BW,LANE_COUNT and LINK_TRAIN_PATRN are 0x14,0x04 and 0x03.

when run the project,the printf informationis:

Cable is disconnect or unplug.
DPCD_LINK_BW_SET is: 0x6
DPCD_LANE_COUNT_SET is: 0x1
DPCD_LINK_TRAIN_PATRN_SET is: 0x0
INTERRUPT CAUSE is: 0x80018002

 

if i remove DP-cable plug,the value of LINK_BW,LANE_COUNT and LINK_TRAIN_PATRN are initial value.

i think the FPGA is trying to link with source ,but link failed,and source(GPU) does not read EDID frome sink.

 

my configuration code is below,the code refer to files "xapp1178.zip" "xapp593_DisplayPort_Sink.zip" and "PG064-Display Port.pdf".

the EDID information is initialized in blockram of FPGA.

 

void main(void)

{

u32  uc;

u32 unplug;
u32 tp1_intrpt;
u32 tp23_intrpt;
u32 tran_done;
u32 lost_tran;
u32 link_bw;
u32 lane_count;
u32 train_patrn;

 

Dp159_reset();

InitIt_Dp159();

dump_ip_info();

policy_maker_init();

dump_video_info();

 

while (1)
{

link_bw=DPSINK_IIC_Read(DPCD_LINK_BW_SET);
lane_count=DPSINK_IIC_Read(DPCD_LANE_COUNT_SET);
intrpt_value=DPSINK_IIC_Read(INTERRUPT_CAUSE);
train_patrn = DPSINK_IIC_Read(DPCD_TRAINING_PATTERN_SET);
xil_printf("DPCD_LINK_BW_SET is: 0x%x\r\r\n", link_bw);
xil_printf("DPCD_LANE_COUNT_SET is: 0x%x\r\r\n", lane_count);
xil_printf("DPCD_LINK_TRAIN_PATRN_SET is: 0x%x\r\r\n", train_patrn);
xil_printf("INTERRUPT CAUSE is: 0x%x\r\r\n", intrpt_value);

tran_done = intrpt_value & 0x04000;
lost_tran = intrpt_value & 0x10;
unplug = intrpt_value & 0x80000000;
tp1_intrpt = intrpt_value & 0x10000;
tp23_intrpt = intrpt_value & 0x60000;

 

if(unplug==0x80000000)
{
ReInitIt_Dp159();
DPSINK_IIC_Write(LINK_ENABLE, 0x00);
delay_nms(10);
DPSINK_IIC_Write(LINK_ENABLE, 0x01);
xil_printf("Cable is disconnect or unplug.\r\r\n");
}
else if(tp1_intrpt==0x10000)
{
Tp1_Intr_Handler(link_bw, lane_count);
xil_printf("Current interrupt is Training pattern 1.\r\r\n");
}
else if(tp23_intrpt != 0x0)
{
Tp23_Intr_Handler();
xil_printf("Current interrupt is Training pattern 2 or Training pattern 3.\r\r\n");
}
else if (tran_done==0x4000)
{
xil_printf("training success.\r\r\n");
}
else if(lost_tran==0x10)
{
DPSINK_IIC_Write(LINK_ENABLE, 0x00);
delay_nms(10);
DPSINK_IIC_Write(LINK_ENABLE, 0x01);
xil_printf("training is lost.\r\r\n");
}

delay_nms(500);

}

 

}

 

void policy_maker_init(void)
{
u32 uc;
DPSINK_IIC_Write(LINK_ENABLE, 0x00); //Disable

DPSINK_IIC_Write(AUX_CLOCK_DIVIDER, 50);
DPSINK_IIC_Write(PHY_CONFIG, 0x03);
DPSINK_IIC_Write(PHY_CONFIG, 0x02);
DPSINK_IIC_Write(CDR_CONTROL_CONFIG,0x1388);
DPSINK_IIC_Write(PHY_CONFIG, 0x3800000);
DPSINK_IIC_Write(MST_CAPABILITY,0x00);
DPSINK_IIC_Write(XILINX_DISPLAYPORT_RX_LOCAL_EDID_VIDEO,0x01);
DPSINK_IIC_Write(SINK_DEV_COUNT,0x01);
DPSINK_IIC_Write(MIN_VOLTAGE_SWING, 0x02);

set_link_rate_and_lanes_capability(0x14,0x4,0x03);

DPSINK_IIC_Write(INTERRUPT_MASK, 0x00);
DPSINK_IIC_Write(LINK_ENABLE, 0x01); 
DPSINK_IIC_Write(USER_PIXEL_WIDTH, 0x4);
DPSINK_IIC_Write(LINE_RESET_DISABLE,0x01);
dpsink_sreset();
delay_nms(50);
DPSINK_IIC_Write(DTG_ENABLE, 0x03);//enable DTG

}

 

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Highlighted
Visitor
Visitor
5,789 Views
Registered: ‎09-09-2015

Re: Xilinx Display Port v6.1 - Rx with dp159 retimer.

Please help me to solve the problems,Thank you very much.

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