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Adventurer
Adventurer
6,349 Views
Registered: ‎04-22-2016

Xilinx FIFO doesn't work as well.

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Hi.

 

I'm trying to use the Xilinx FIFO as below, but I can't understand why dout is stopping at that point?

The fifo doesn't work anymore at that point.

Does anyone know how to resolve this problem?

 

I just let you know, aclk, wr_clk are 192Mhz, bclk, rd_clk are 100Mhz.

 

114.jpg

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Adventurer
Adventurer
12,383 Views
Registered: ‎04-22-2016

Re: Xilinx FIFO doesn't work as well.

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I mean that point is 4.5ns after. as you can see. dout does not work at that point.
Also, as you can see that, wr_en is high then read_en is hight after reset. write clock is 192mhz and read clock is 100Mhz.
Generally, write clock is more faster than read clock. it tells that dout should be not stop.
I can't understand why empty is going to high? write clock is more faster than read clock.
WR_EN and RD_EN have to work as exclusively?
Can you explain that empty signal is going to high while input data keep in to input?
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Teacher muzaffer
Teacher
6,316 Views
Registered: ‎03-31-2012

Re: Xilinx FIFO doesn't work as well.

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I not sure what you mean by 'dout is stopping at that point' as 'that point' is not clear but it seems to me dout works nicely.
You write to fifo for a while and you read from it later. You have empty go low, dout starts toggling, rd_data_count does toggles til empty becomes high which means fifo thinks you read all the data.
What do you think is the problem? Are you counting how many items you put in the fifo vs how many you take out? Are they not the same?
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Adventurer
Adventurer
12,384 Views
Registered: ‎04-22-2016

Re: Xilinx FIFO doesn't work as well.

Jump to solution
I mean that point is 4.5ns after. as you can see. dout does not work at that point.
Also, as you can see that, wr_en is high then read_en is hight after reset. write clock is 192mhz and read clock is 100Mhz.
Generally, write clock is more faster than read clock. it tells that dout should be not stop.
I can't understand why empty is going to high? write clock is more faster than read clock.
WR_EN and RD_EN have to work as exclusively?
Can you explain that empty signal is going to high while input data keep in to input?
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Teacher muzaffer
Teacher
6,237 Views
Registered: ‎03-31-2012

Re: Xilinx FIFO doesn't work as well.

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I guess your issue is resolved but I am not sure what the solution was.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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