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Observer
Observer
6,951 Views
Registered: ‎04-24-2012

Xst:772 : Attribute is not authorized : 'val'.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity int_to_bitv is
    generic( n : integer := 8);
    port( in_int : integer;
            out_bitv : out bit_vector(n-1 downto 0)
            );
end int_to_bitv;

architecture Behavioral of int_to_bitv is
--This function is used to convert integer input to bit vector type in 2's complement form
    function int_to_bitv(in_int : integer) return bit_vector is
        variable temp : integer;
        variable result : bit_vector(n-1 downto 0);
    begin
        if(in_int < 0) then
            temp := -(in_int + 1);
        else
            temp := temp;
        end if;
        
        for index in 0 to n-1  loop
            result(index) := bit'val(natural'(temp rem 2)); --ERROR HERE
            temp := temp / 2;
        end loop;
        
        if in_int < 0 then
            result := not result;
            result(n-1) := '1';
        end if;
        
        return result;
    end function;
begin
    out_bitv <= int_to_bitv(in_int);
end Behavioral;


ERROR:Xst:772 - "E:/Study/Codes and Designs/Xilinx_workspace/Third/int_to_bitv.vhd" line 24: Attribute is not authorized : 'val'.

 

This error was given to to me by XST. Syntax check was fine.

 

The code was written to check a simple function.

I do not understand what this error means. The attribute is given in the language templates and I have seen it in my books. I don't see any error. So what's the problem?

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Scholar
Scholar
6,946 Views
Registered: ‎02-27-2008

Re: Xst:772 : Attribute is not authorized : 'val'.

bit'val?

 

What is that supposed to mean (to do)?

 

I don't see any val in any verilog reference anywhere, and I don't see it used (defined).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Historian
Historian
6,937 Views
Registered: ‎02-25-2008

Re: Xst:772 : Attribute is not authorized : 'val'.


@austin wrote:

bit'val?

 

What is that supposed to mean (to do)?

 

I don't see any val in any verilog reference anywhere, and I don't see it used (defined).

 

 


It's VHDL. 

 

The 'val attribute, when used with a scalar type (such as bit), returns the "value at position x in T."

 

The VHDL type bit is defined as:

 

type bit is ('0', '1');  -- defined in the std library

 

so bit'val(0) will return '0' and bit'val(1) will return '1', and it should be obvious that '0' is not the same as 0.

 

{Conversely, the 'pos attribute returns the position in the type definition, so bit'pos('0') will return 0 and bit'pos('1') will return 1.}

 

Having said all of that, I'm not sure why XST throws that error. The argument for the 'val attribute is an integer. I suppose he's doing the cast to natural to ensure that the argument to the 'val attribute is non-negative, although he takes care of that in the if statement that preceeds the loop over the result vector.

 

Perhaps creating another variable called remainder and precalculating it before using it in the attribute might clarify things.

 

    for index in result'range loop

        remainder := temp rem 2;

        result(index) := bit'val(remainer);

        temp := temp / 2;

    end loop;

 

good luck.

----------------------------Yes, I do this for a living.
Highlighted
Observer
Observer
6,927 Views
Registered: ‎04-24-2012

Re: Xst:772 : Attribute is not authorized : 'val'.

       
        for index in 0 to n-1  loop
            remainder := temp rem 2;
            result(index) := bit'val(remainder);
            temp := temp / 2;
        end loop;
       


Wrote this and ran it. Same problem.

 

Is there some list of errors which can explain these cryptic error messages? Instead of asking these on forum I'll just download the whole thing.

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Observer
Observer
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Registered: ‎04-24-2012

HDLCompiler:183 : A homograph of int_to_bitv is already declared in this region

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity int_to_bitv is
    generic( n : integer := 8);
    port( in_int : integer;
            out_bitv : out bit_vector(n-1 downto 0)
            );
end int_to_bitv;

architecture Behavioral of int_to_bitv is
--This function is used to convert integer input to bit vector type in 2's complement form
    procedure int_to_bitv(signal in_int : integer; signal bits: out bit_vector)is --ERROR HERE
        variable temp : integer := in_int;
        variable result : bit_vector(bits'range);
    begin
        if(temp < 0) then
            result(bits'high) := '1';
            temp := temp - 2**(bits'high);
        else
            result(bits'high) := '0';
        end if;
        
        for i in (bits'high)-1 downto 0 loop
            if(temp >= 2**i) then
                result(i) := '1';
            else
                result(i) := '0';
            end if;
            temp := temp / 2;
        end loop;
        bits <= result;
    end procedure;
begin
    int_to_bitv(in_int, out_bitv);
end Behavioral;



I wrote another one to do the conversion. I got

 

HDLCompiler:183 : A homograph of int_to_bitv is already declared in this region

 

Now what is a homograph?

Anyone?

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Teacher
Teacher
6,913 Views
Registered: ‎09-09-2010

Re: HDLCompiler:183 : A homograph of int_to_bitv is already declared in this region

http://dictionary.reference.com/browse/homograph?s=t

And if I get a bit of time this afternoon, I'll look at the code in some detail. I seem to recall having a problem with 'val at some point in the past...

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Teacher
Teacher
6,911 Views
Registered: ‎09-09-2010

Re: Xst:772 : Attribute is not authorized : 'val'.

What about:

 

library IEEE;
use IEEE.numeric_bit.all;

entity int_to_bitv is
generic( n : integer := 8);
port( 
  in_int : integer;
  out_bitv : out bit_vector(n-1 downto 0)
);
end entity int_to_bitv;

architecture functional of int_to_bitv is
--To convert integer input to bit vector type in 2's complement form,
--therefore assumed can be negative.
begin

  out_bitv  <=  bit_vector(to_signed(in_int, n));

end architecture functional;

 

Or is that too easy?

 


------------------------------------------
"If it don't work in simulation, it won't work on the board."
Highlighted
Observer
Observer
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Registered: ‎04-24-2012

Thanx

Is there some document in which the conversion functions are given? It took me huge time to write this whole thing. The language templates only contain conversion functions for std_logic.

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Historian
Historian
6,901 Views
Registered: ‎02-25-2008

Re: HDLCompiler:183 : A homograph of int_to_bitv is already declared in this region


@zelalex wrote:

 


I wrote another one to do the conversion. I got

 

HDLCompiler:183 : A homograph of int_to_bitv is already declared in this region

 

Now what is a homograph?

Anyone?


From the VHDL LRM:

 

B.117 homograph: A reflexive property of two declarations. Each of two declarations is said to be a
homograph of the other if both declarations have the same identifier and overloading is allowed for at most

one of the two. If overloading is allowed for both declarations, then each of the two is a homograph of theother if they have the same identifier, operator symbol, or character literal, as well as the same parameter andresult type profile. (§1.3.1,§10.3

 

In other words: VHDL allows you to overload functions and operators. This is how the + operator, for example, can work with all sorts of different types. Browse through the source code for numeric_std, for example, and you'll see functions declared for + with signed arguments, unsigned arguments, integer arguments, etc. Obviously, the arguments and the return value for each flavor are different; as such, they are not homographs.

 

So a homograph is basically a duplicate declaration. And for whatever reason, you appear to have to declarations for your conversion function.

 


----------------------------Yes, I do this for a living.
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Historian
Historian
6,899 Views
Registered: ‎02-25-2008

Re: Thanx


@zelalex wrote:

Is there some document in which the conversion functions are given? It took me huge time to write this whole thing. The language templates only contain conversion functions for std_logic.


The source for numeric_std and for std_logic_1164 includes a bunch of conversions.

 

also, see here (pdf).

 

And every good VHDL textbook discusses this sort of thing. Most of us seem to like Ashenden's book.

----------------------------Yes, I do this for a living.
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Scholar
Scholar
2,211 Views
Registered: ‎02-27-2008

Re: Thanx

All,

 

I just ran across this in an internal bug report for 14.1.  Evidently it has been fixed....

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Historian
Historian
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Registered: ‎02-25-2008

Re: Thanx


@austin wrote:

All,

 

I just ran across this in an internal bug report for 14.1.  Evidently it has been fixed....

 

 


Good deal. This is one of the dusty corners of VHDL into which few users peek, and as such, nobody's run into this particular bug.

----------------------------Yes, I do this for a living.
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