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Registered: ‎12-23-2013

Zero Padding IFFT calculation

Dear all, 


I am sorry I am not sure whether I should ask such question in Xilinx forum !


I want to calculate the IFFT of a data in such format (D1 Z D2) where D1 and D2 is n complex data and Z  is many zeroes which is inserted in between of my data (known as zero-padding). The size of D1 and D2 is 13920 and 13921 respectively. The number of zeroes is 103231. So the data size for the IFFT is 128K. The maximum IFFT length in Xilinx IP Core is 64k. Therefore I used two 65K IFFT modules and now everything is working fine. My question is; is there any simpler way to calculate the IFFT with smaller IFFT module?

I am not familiar with communication concepts very much, but I see the problem from mathematical point of view. As most of the data is zero so there should be a more efficient way of calculating data both in terms of speed and area.


I do highly appreciate it if anyone who can suggest me a solution.


Many Thanks,

Shervin Zargham 

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