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Registered: ‎08-22-2012

Zynq 7000 FUSE_CNTL[1] Register, AES_Exclusive Bit

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Does setting the AES_Exclusive Bit in the Zynq 7000 FUSE_CNTL[1] register prevent partial reconfiguration of the programmable logic from the processing system?

rickster
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stevem
Xilinx Employee
Xilinx Employee
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Registered: ‎07-23-2015

If you set this bit it disables Partial Reconfiguration (PR) from external configuration interfaces.  However, you can still do PR using the internal interface (i.e. ICAP port aka ICAPE2).  Reference UG470 (V1.1) on page 99:

 

http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

 

Steve

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stevem
Xilinx Employee
Xilinx Employee
3,313 Views
Registered: ‎07-23-2015

If you set this bit it disables Partial Reconfiguration (PR) from external configuration interfaces.  However, you can still do PR using the internal interface (i.e. ICAP port aka ICAPE2).  Reference UG470 (V1.1) on page 99:

 

http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf

 

Steve

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