I'm working on a PR project with ZYBO. I use Xilinx ISE 14.6 and i have some difficulties to generate my ucf file and if i try to access to "I/O planning (PlanAhead) - Post Synthesis" I have this message :
" Unable to get a license. There may be a problem with your FLEXNet configuration, or your license server may be down. What would you like to do ---> Retry; Get license... and Exit".
I don't really understand because I have a valid license.
In the UCF file, I have a top module which contains clk (10 ns) reset (valid on high) and output(4 bits). I would like to connect my clk and my reset to the system clock and system reset. And connect the output data to the Leds (M14; M15; G14; D18).