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kpench
Contributor
Contributor
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Registered: ‎01-07-2015

Zynq XC7Z020 - DDR3 design with ECC supp

Hi

 

We are planning to use the DDR3 inbuilt controller of XC7Z020 PS section to interface it to 2 chips [MT41K128M16] -32-bit data width.  we are planning to use one more DDR3 component to support ECC.

 

Please let us know the DDR3 controller pins details in XC7Z020 PS including ECC pin details.

 

Thanks

Pench

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vsrunga
Xilinx Employee
Xilinx Employee
2,791 Views
Registered: ‎07-11-2011

HI,

 

I do not think there are separate ECC pins, please visit below link and go to ASCII files for pin loations of your package

 

http://www.xilinx.com/support/documentation/user_guides/ug865-Zynq-7000-Pkg-Pinout.pdf

 

http://www.xilinx.com/support/packagefiles/z7packages/xc7z020clg484pkg.txt

 

http://www.xilinx.com/support/packagefiles/z7packages/xc7z020clg400pkg.txt

 

 

Also go through below AR for ECC test example design

http://www.xilinx.com/support/answers/58684.html

 

 

Hope this helps

 

-Vanitha

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kpench
Contributor
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Registered: ‎01-07-2015

Hi

 

Thanks for the info.

 

I could not able to find any dedicated DDR3 ECC pins in the package.

Is it will be internally supported?

 

Please let me know.

 

Thanks

Pench

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vsrunga
Xilinx Employee
Xilinx Employee
2,780 Views
Registered: ‎07-11-2011

Hi,

 

Yes, there are no dedicated ECC pins,  controller takes care of the opeartion. PSDDR uses lower 16bit as data and few higer bits for ECC.

Please refer UG585  0.8 Error Correction Code (ECC) section for more details.

 

PSDDR_ECC.png

 

 

Hope this helps

 

-Vanitha 

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kpench
Contributor
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Registered: ‎01-07-2015

Hi

 

U mean no need of external DDR3 component for the ECC operation right?

 

Thanks

Pench

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vsrunga
Xilinx Employee
Xilinx Employee
2,763 Views
Registered: ‎07-11-2011

Hi,

 

External DDR3 interface and data is needed but the component by itself do not play any role in ECC functionality, it stores all normal data and ECC bits as data

 

Regards,

Vanitha

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