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Visitor
Visitor
2,654 Views
Registered: ‎04-19-2014

Zynq open collector output stuck

I'm trying to implement an open collector in Verilog but it gets stuck outputting 0.

 


 

module ... (inout wire sdcka, sdckb)...

 

always @(posedge aclk) begin: SDCKX_OUTPUT_ENABLE
  if (aresetn == 1'b0) begin
    sdcka_oe = 0;
    sdckb_oe = 0;
  end else begin
    sdcka_oe = (enable_loopback == 0 && transmitting == 1 && sdcka_tx == 0);
    sdckb_oe = (enable_loopback == 0 && transmitting == 1 && sdckb_tx == 0);
  end
end


assign sdcka = sdcka_oe ? 1'b0 : 1'bz;
assign sdckb = sdckb_oe ? 1'b0 : 1'bz;

 

always @(posedge aclk) begin: SDCKX_SYNC
  sdcka_sync = sdcka;
  sdckb_sync = sdckb;
end


 

 

sdcka and sdckb are connected to a bus with an external pull up resistor. Using the ILA I looked at the signals and I see that the sdcka_oe signal is correct. If I look at the sdcka_sync signal it gets pulled to GND for the duration of transmission. If I use an external logic analyzer and probe the sdcka pin I see the same thing. I want to let the external pull up resistor drive the 1 value on the bus and only drive the 0 value from the FPGA. What am I doing wrong?


Thanks,
Raul

Xilinx Dev-2015-01-11-11-41-27.png
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Teacher
Teacher
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Registered: ‎03-31-2012

who else is driving the sdck wires? what's the value of the pull-up resistors on these wires? wire sdck_oe signals constantly to active (high) and make sure that the external wires are high by begin pulled up. If not, the other chip is pull them low.
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Visitor
Visitor
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Registered: ‎04-19-2014

The sdck master is the only other device attached to the wires. I'm not 100% sure what the pull up resistor value is. I can confirm it's enough for the master to transmit, and for the FPGA and my external logic analyzer to be able to read the signal. So I'm making the assumption that if I can receive data I should be able to transmit data.

 

If you look at the ILA capture before sdcka_oe goes HIGH you can see that sdcka_sync is HIGH. The same is true for my external logic analyzer. I'm pretty sure the master is not pulling the wires low because sdcka_sync goes LOW when sdcka_oe goes HIGH.

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Teacher
Teacher
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Registered: ‎03-31-2012

>> The sdck master is the only other device attached to the wires
the fpga logic you show above is the master right? so the external pins are not connected to any slave yet?

another question is how long the low period of sdck signals are. are you allowing the pull-up enough time to pull?
finally try making the sdck_oe reg be assigned to the io slot ie add (* iob = "true" *) reg sdcka_oe;
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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Since the SDA/SCK (sync) inputs are a logic 1 to begin with and then transition to a logic 0 after the the first driving of a logic 0 (oe=1) the problem is likely that the rise time of the weak pullup on the board is too slow and it doesn't get to 70% of VCCO by the time that the input is sampled.   This could either be due to a very weak (should be less than 5Kohm) pullup to VCCO or that the ACLK that you are using is too fast (should be less than 400 KHz, and usually less than 100 KHz).

 

My bet is that it is the latter condition and ACLK is running too fast.

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