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5,492 Views
Registered: ‎09-07-2015

adding combinatorial logic to viviado block design

Newbie Vivado question...

I need a small glue-logic circuit within my block design. 

I was wondering if there's a quick way to add a combinatorial circuit into a Viavdo block design without using HLS or designing a custom IP.  Is there a Logicore IP that allows a logic table lookup or writing a few lines of VHDL code into the block?

 

 

 

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10 Replies
rjsefton
Explorer
Explorer
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Registered: ‎11-25-2014

One approach is to not put it in the BD. Instead, do it in the top-level HDL wrapper that instantiates the BD. You'll need to modify the BD to make whatever signals go into your comb. logic output ports from the BD and create an input port in the BD to connect the output of your comb. logic. That's the way I would do it, but others may have other recommendations.

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athandr
Xilinx Employee
Xilinx Employee
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Registered: ‎07-31-2012

You can create your own IP with the custom combincatorial code. you can check the below docs for help

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug1119-vivado-creating-packaging-ip-tutorial.pdf

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug994-vivado-ip-subsystems.pdf

 

 

Thanks,
Anirudh

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5,459 Views
Registered: ‎09-07-2015

I was afraid that someone would suggest this. It would probably work but defeats the purpose of having a block design. The problem is, It would make reading the block design difficult, looping in and out of ports, specially for small glue logic between blocks.

 

Thanks, for confirming.

 

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morgan198510
Voyager
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Registered: ‎04-21-2014


@mchoudhury@aphysci.com wrote:

I was afraid that someone would suggest this. It would probably work but defeats the purpose of having a block design. The problem is, It would make reading the block design difficult, looping in and out of ports, specially for small glue logic between blocks.

 

Thanks, for confirming.

 


Did you read what @athandr wrote?  You don't have to edit the top level (and I would not recommend editing the top level, as you're right, it defeats the purpose.). 

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rjsefton
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Registered: ‎11-25-2014

The OP was trying to avoid creating custom IP, and I share the same aversion. For me the BD is a necessary evil for zynq designs. I much prefer to work in the HDL domain.

 

How does routing signals in and out of the BD defeats its purpose? IMO the purpose of the BD is to provide a convenient way to set up the PS and its connections to the PL. Can't imagine doing the entire design in that environment.

 

By the way, I wasn't talking about editing the DB wrapper that Vivado conveniently generates. I was talking about the level above that where the BD wrapper is instantiated (at least in my world).

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morgan198510
Voyager
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Registered: ‎04-21-2014


@rjsefton wrote:

 

By the way, I wasn't talking about editing the DB wrapper that Vivado conveniently generates. I was talking about the level above that where the BD wrapper is instantiated (at least in my world).


Yeah, if you're set on editing above the .bd, that is the way to do it (wrap the auto-generated wrapper).  Sorry I missed that. 

 

Structural coding via VHDL or Verilog was once necessary.  But I don't think it will scale well going into the future.  But it takes time for experienced engineers to give up there favorite methods.  I still like DOS, for example, especially the ability to access low level IO without having to go through the OS abstractions that now exist.  :)

 

Anyway, things keep changing in this field, I don't expect that will stop.

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rjsefton
Explorer
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Registered: ‎11-25-2014

This thread has now been officially hijacked, but I think discussions like this about different ways to get things done in Vivado are very useful for people just getting started with it (like me). The IPI/BD approach of stitching together blocks of IP to create a design is central to the whole concept and structure of Vivado. Unfortunately, that means that all of the vast Vivado documentation, including reference designs, methodology guides, etc., push that approach while alternate approaches, for the most part, are not even mentioned.

 

I'm personally nowhere near ready to declare the hierarchical HDL approach dead or even close to running out of gas. It's got plenty of legs left, especially for the kinds of designs I do. I don't avoid the graphical approach just because I'm a crusty old dude set in my ways (which is true). I just don't find that the graphical approach makes me any more productive at this point. That could easily change on future projects, but for now I'll stick with what I'm doing.

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athandr
Xilinx Employee
Xilinx Employee
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Registered: ‎07-31-2012

IPI designs are mostly used for processor based application - This is a replacement for XPS in ISE.

 

We still have the HDL flow active, where we have a separate library of IP's usign IP catalog. And also there are n number of designs out there only based on HDL flow, if you can find them.

 

However i guess coming to the main topic, the only way to add additional combinatorial logic (if you dont want to create on more IP) is to write it above the wrapper file.

Thanks,
Anirudh

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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

Actually BD is not necessary for Zynq designs. You can do everything as before, ie use your own top level rtl module and makefile etc.
If you want to use a BD just for top level with DDR automation etc. you can create a very simple BD with a single block of IP to take all of your AXI connectivity and work on rtl of that simple big chunk from then.
Again, you can do everything without a BD or create a single large chunk of ip which does everything you need.
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muzaffer
Teacher
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Registered: ‎03-31-2012

Unfortunately BD editor is not a schematic design tool but there is still some hope:
Check-out "utility reduced logic", "utility vector logic", "slice" & "concat" ip blocks. It is messy but you should be able to write any combinational logic with these blocks.
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