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Visitor gpr_123
Visitor
10,268 Views
Registered: ‎03-25-2016

bitstreem error for kintex 7 fpga

Hi,I am using vivado2014.2 version .

 

 

 

ERROR: [Drc 23-20] Rule violation (LUTLP-1) Combinatorial Loop - 1 LUT cells form a combinatorial loop.
This can create a race condition. Timing analysis may not be accurate.
The preferred resolution is to modify the design to remove combinatorial logic loops.
To allow bitstream creation for designs with combinatorial logic loops (not recommended),
use this command: set_property SEVERITY {Warning} [get_drc_checks LUTLP-1].
NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file
and add that file as a pre-hook for write_bitstream step for the
implementation run. ddr_adc_i/axi_only6_0/U0/data_out_ADC2_reg[13]_i_1.

bitstream error

[Drc 23-20] Rule violation (LUTLP-1) Combinatorial Loop - 1 LUT cells form a combinatorial loop.
This can create a race condition. Timing analysis may not be accurate.
The preferred resolution is to modify the design to remove combinatorial logic loops.
 To allow bitstream creation for designs with combinatorial logic loops (not recommended),
 use this command: set_property SEVERITY {Warning} [get_drc_checks LUTLP-1].
NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file
and add that file as a pre-hook for write_bitstream step for the implementation run.
 ddr_adc_i/axi_only6_0/U0/data_out_ADC2_reg[13]_i_1.

[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

 

 

 

axi_only6_0  is the IP Core that Ihave created

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3 Replies
Explorer
Explorer
10,257 Views
Registered: ‎10-14-2015

Re: bitstreem error for kintex 7 fpga

Hi @gpr_123

 

Please see the discussion

 

https://forums.xilinx.com/t5/Implementation/DRC-23-20-Rule-Violation-LUTLP-1/m-p/674253/highlight/true#M14370

 

Thanks,

Sarada

 

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Xilinx Employee
Xilinx Employee
10,256 Views
Registered: ‎07-21-2014

Re: bitstreem error for kintex 7 fpga

Hi,

As error clearly states, your code is creating a combinatorial loop.
Can you open Elaborated/synthesized design and see which portion of your code is creating this?
axi_only6_0 seems to be the custom IP.

Please search the portion of code which is creating this loop.

-Shreyas Aher
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Visitor gpr_123
Visitor
10,185 Views
Registered: ‎03-25-2016

Re: bitstreem error for kintex 7 fpga

Hi Shreyas Aher

     yes,axi_only6_0   is the IP that i have created and attached to the required block diagarm. I have seperated adc reading logic code with AXI interface and generated ip  then there is no error in bitstreem, but when i am including adc Reading logic and after generated IP then added to block diagram i am facing  bit streem error  i.e, combinatorial loop

 

 

Thanx

gpr

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