01-22-2017 11:22 AM
I am using vivado 2016.4 for synthesis of my code. It don't give any error . But I am unable to synthesize it. I don't know why program is running infinetly. my code is given in attached image. I am trying to synthesize it for genesys 2 board. Can you please help me why it is not synthsizing? and what should I do?
01-22-2017 11:31 AM - edited 01-24-2017 01:39 PM
You are declaring what is, in essence a 2 million bit array of bits (640x480x8). You are trying to write to it as a 2 dimensional array of 8bits, and you are trying to read four 8 bit words at the same time each clock.
While this may be doable in block RAM if implemented properly, you are not using a recommended syntax for inferring RAMs and you are not explicitly coding in a way that allows the tools to figure out which ports of the RAMs are to be used under what conditions. This is in addition to the odd "wait until rising_edge(CLK);" syntax which (I am not a VHDL expert) is not the normal way to infer clocked logic.
My assumption is that it can't recognize the RAM, and is, instead, attempting to build an array of 2 million flip-flops which, in addition too being way to big for the device, is choking the synthesis tool (which has probably run out of memory and is swapping your machine).
Refer to the language templates for the proper way to infer dual port RAMs.
01-22-2017 02:49 PM
In addition to what @avrumw has said, while situations do exist where buffering a whole image on-chip makes sense, those situations are fairly rare (normally when you need random access to lots of pixels in each clock cycle). If your data access is going to be sequential (as it normally is, for image processing) or can be made sequential with a bit of buffering, then storing it in off-chip RAM will drastically cut down your on-chip resources.
01-24-2017 11:55 AM
Can you please tell me from where I can learn about effective RAM coding styles?
01-24-2017 01:38 PM
The Vivado Synthesis User Guide (UG901) provides some description (and mostly a link to some examples) in Chapter 3; there is a section called RAM HDL Coding Techniques.
You can also find some examples in the language templates from the tool. With a project open you can go
Tools -> Language Templates -> Verilog/VHDL -> Synthesis Constructs -> Coding Examples -> RAM