crc generator according xapp209

[amin5659]

hi all .
I'm trying to generate crc code from sting of data.
for that reason i generated this hard ware based xilinx app note and this site :
https://www.ghsi.de/CRC/


but when i test this HDL design with this ethernet frame i get different result
this is ethernet frame from fpga4fun :
http://www.fpga4fun.com/10BASE-T2.html
55 55 55 55 55 55 55 D5 00 10 A4 7B EA 80 00 12 34 56 78 90 08 00 45 00 00 2E B3 FE 00 00 80 11 05 40 C0 A8 00 2C C0 A8 00 04 04 00 04 00 00 1A 2D E8 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 B3 31 88 1B
" B3 31 88 1B " => this is true crc code.
but i get this :"42 76 f0 4e"
i just shift data string in LFSR.
where is wrong??

[amin5659]

please help guide me guys ...

I'm waiting

[allanherriman]

You might be waiting a long time if you expect forum posters to be able to work out the faults in your logic from just a big string of hex digits.

Please check the following:

• You should not include the preamble/SFD in the CRC.  By this I mean you should ignore the "55 55 55 55 55 55 55 D5" at the start.
• The CRC register (by that I mean those flip flops in your schematic) must be initialised to all ones at the start of the frame before you starting clocking data into it.  (There are also other, equivalent ways of achieving the same result, such as initialising the register to all zeros and inverting the first 32 bits of the data.)
• The bit order of each byte going into the CRC is LSB first.  i.e. your third byte, hex A4, is the bit string (first to last) 00100101.
• The CRC result is inverted.  Ones become zeros and zeros become ones.
• Depending on how you've numbered the bits, you may need to reverse the order of bits and/or bytes in the CRC register to get the final result.

Perhaps your answer is in there somewhere.

Allan