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deepakmmathew
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Registered: ‎10-02-2015

debug hub core not detected

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Hi,

I am testing the MIG ultrascale memory controller (Version 2.1) on a Virtex ultrascale device. From the LED indications, the controller works fine on the board. But I couldn't see any calibration status signals from the Microblaze core inside the PHY due to the following error:

 

INFO: [Labtools 27-1434] Device xcvu095 (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].

 

Since this is error is reported in the forum many times before, I have checked all the previous solutions and summarized below:

1. The debug_hub is correctly clocked -- i have connected this clock to an LED to confirm this

2.  The debug hub core is present in the implemented design at USER_SCAN_CHAIN '1'

3. The JTAG clock frequency is lower than debug_hub clock

 

Can anyone help me in debugging this?

 

 

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deepakmmathew
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Registered: ‎10-02-2015

Finally I found the issue. There was a version mismatch between Vivado  hardware manager and the Vivado design suite version which was used to create the project. The hardware manager installed on my local machine was 2015.3, while the project was created on the server using vivado 2016.4. I never expected this to be a problem since the bitstream was loaded successfully to the FPGA.  

@Xilinx  please make the warnings clear. There could have been a warning stating the version difference. 

 

Thank you all for your suggestions.

 

Thanks,

Deepak

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a_chami
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Registered: ‎04-12-2017

@deepakmmathew

 

I work with Zynq. If I use a clock coming from the Zynq for the ILA, I have to initialize it first.

 

I will usually receive the message because the .bit download finishes before I have a chance to init the Zynq. But after I have initialized the Zynq (via the SDK), I refresh the target on the Hardware Manager and that solves the 'no clocking' issue.

 

Hope that you can do something similar in your configuration.

 

Avi Chami MSc
FPGA Site
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deepakmmathew
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Registered: ‎10-02-2015
But in my case I work only with PL side. So, no initialization is needed. The debug clock is coming directly from the MIG controller. Also I tried refreshing hardware manager too.. it didn't fix the issue
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vemulad
Xilinx Employee
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Registered: ‎09-20-2012

Hi @deepakmmathew

 

Are you driving the MIG ui_clk output to debug hub?

 

How are the sys_clk and sys_rst inputs of the MIG IP core driven? Is the sys_rst asserted and de-asserted properly?

Thanks,
Deepika.
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deepakmmathew
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Registered: ‎10-02-2015

Hi @vemulad,

 

Yes. dbg_clk, which is the same as MIG ui_clk is connected to the debug hub.

 

sys_clk and sys_rst are correctly assigned, since the design is working correctly on the board. The board LEDs indicate that.

 

But, neither the debug signals that I have inserted nor the Microblaze status signals (PHY) don't work. 

 

 

 

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arpansur
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8,991 Views
Registered: ‎07-01-2015

Hi @deepakmmathew,

 

  1. Is it VCU108 board? If so can you please try with configurable mb example design and insert ILA to it and see if you are still seeing the issue?
  2. Try using free running clock and see if the issue persists.
  3. What are the frequency of the clocks?
Thanks,
Arpan
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vemulad
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Registered: ‎09-20-2012

Hi @deepakmmathew

 

What is the status of MIG in HW manager? Is the calibration successful?

Thanks,
Deepika.
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deepakmmathew
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Registered: ‎10-02-2015

Finally I found the issue. There was a version mismatch between Vivado  hardware manager and the Vivado design suite version which was used to create the project. The hardware manager installed on my local machine was 2015.3, while the project was created on the server using vivado 2016.4. I never expected this to be a problem since the bitstream was loaded successfully to the FPGA.  

@Xilinx  please make the warnings clear. There could have been a warning stating the version difference. 

 

Thank you all for your suggestions.

 

Thanks,

Deepak

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