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Contributor
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Registered: ‎04-12-2017

design works in simulation but not hardware

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Hi all,

First things first, I’m fairly new to FPGA design, so don’t judge me.

 

I’m currently working on a very simple design which (in theory) calculates pi (actually pi/4). It consists of a pipeline of double precision floating point ip cores (adders, reciprocals, accumulators) which feeds into block design containing a microblaze which outputs the result to the uart.

The design works perfectly fine in the behavioral simulation, it meets all timing requirements and I don’t get any critical warnings. The only problem is that it doesn’t work on the hardware (a Digilent Nexys Video powered by an Artix 7 XC7A200T). I tried using an on-chip debugger and thus found out that the result of the pipeline isn’t synchronous to the clock, it just bounces around randomly (as you can see in the attached picture) which makes me think that my timing constraints are incorrect.

I also tried running a post synthesis and post implementation simulation, but all I get are empty windows.

 

I hope someone out there can help me with my problem,

thanks in advance.

sim_vs_hardware.png
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Contributor
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Registered: ‎04-12-2017

Sorry for posting this in Welcome & Join.

If you want to reply, please do it here.

View solution in original post

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Contributor
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3,407 Views
Registered: ‎04-12-2017

Sorry for posting this in Welcome & Join.

If you want to reply, please do it here.

View solution in original post

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