12-12-2016 06:13 AM
hi I am new to this field in vhdl and using vivado for first time.
i am customizing my FFT Ip core with following details
Data format: Fixed point,
Scaling Option: scaled,
Rounding Modes: Truncation,
Input Data width: 16,
Phase Factor width: 16,
Output ordering Option: Natural Order
the input s_axis_tdata has real and imaginary bit of 16 bit.
I have input data as decimal value eg:-22.000000 464.000000 46.000000 -431.000000
how do i convert the above value to fixed point format which the FFT IP core takes
And i want to put this value inside the block ram.. so that i can take 16 bit input directly from ram
i am using fixed point to use less hardware in fpga.
plz answer to my queries
thank u
12-12-2016 10:48 PM
max of abs is 512.344, 32767/512.344 = 63.955 which is the scale you should use.
12-12-2016 09:20 PM
gaonkar@123 as long as your numbers are within the range [-32768 ... 32767] you can just use the integer portion of the numbers you have as input to the FFT block.
12-12-2016 09:42 PM
what about the fractional part.
eg my input in decimal is 145.158 what will the equivalent 16 bit fixed point value be for fft ip input for real and imaginary???
12-12-2016 10:09 PM
gaonkar@123 figure out the max value(s) in your input and find a scale value which adjusts that value to 32767 then take the integer parts of the results. This will use the dynamic range of the FFT maximally.
IOW, if the maximum of the absolute value is 4000 multiple all numbers with 8.192 (=32768 /4000). This will shift all the fractional numbers you can use into the integer range.
12-12-2016 10:29 PM
my maximum negative value is -427.123
and max positive value is 512.344
than what should my scaling be??
12-12-2016 10:48 PM
max of abs is 512.344, 32767/512.344 = 63.955 which is the scale you should use.
12-13-2016 05:36 AM
i have done with it..but my matlab result and vhdl simulation result are not maching
12-13-2016 08:41 AM
did you scale the output back ? FFT(a*x(t)) == a*FFT(x(t))
12-18-2016 09:31 PM
hi.
i scaled it back.. my matlab and vhdl results are matching but real output of vhdl is coming as negation of real value of matlab.
all though the imaginary values of both are matching.
what may be the problem??
thank u.