I send this email to report an error in the System Generator tool for Xilinx. I need your support to resolve it. The problem is when I INtend test the co-simulation block. When I try run it, the response is always “0”.
I thought that the problem was in the system created. For that, only to verify the way that the co-simulation block works, I created a simple design (see the next figure -> it consists in deceiving two input and make a multiplication).
To create a co-simulation block with a board Zynq-7000 EPP 7Z020 ZedBoard Kit, I selected the option as you can see in the next figure.
I clicked on “Generate” and the co-simulation block was created. When I try to test it (see the next figure), I see that the board was programmed (because the blue LED was on) but it is not working (I try select and unselect the option “Reset Zynq board before reconfiguration”).
To understand why it does not work, I explore the co-simulation block and I detect some irregularities. The option “clock source” do not appears, it only appears when I click right on the option “has combinational path (Define with expression)”. It makes no sense. The video in attachment shows what I described. Can you tell me what the problem is? I hope that you can help to resolve this problem.