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2,963 Views
Registered: ‎12-14-2015

error while synthesize. signal can't be synthesized.

Hello,

 

I am working in a wishborne bus and I have the next problem when I synthetize:

 

line 122: Signal data<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

 

The problem is here:

 

process (RST_I, DATp_I, DATm_I, cnt2)  this is line 122.
   begin
        if (rising_edge(RST_I)) then
              cnt <= 0;
             data <= (others => '0');
       elsif (rising_edge(DATp_I) and cnt <4) then
            data(cnt) <= DATp_I;       here is where could be the problem when inicialized.
            cnt<= cnt+1;
      elsif (rising_edge(DATm_I) and cnt <4)then
           cnt<= cnt+1;
          data(cnt) <= DATm_I;
     elsif (cnt2 = count_module) then
          cnt <= 0;
          data <= (others => '0');
    end if;
end process;

 

I have searched at the forum for similar errors and i get into someone who had a problem of the priority with the clock event and the process. I triyed to change my program with the indications are given to him but it doesn't work.

 

Thank you very much.

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muzaffer
Teacher
Teacher
2,960 Views
Registered: ‎03-31-2012

please don't post the same question multiple times.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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