error with setting 64 bit BRAM

[novec_16]

My tool is Vivado 2016.4, hardware is a development board with Zynq 7010.

I have good results when utilized IP Block Memory Generator 32bit wide 32kB depth True Dual BRAM.

One port is used to connect to PS (READ_FIRST) and the second to PL (WRITE_FIRST).

Now I am trying to change the data width from 32 bits to 64 bits and having three error messages:

• [IP_Flow 19-3461] Value '32' is out of the range for parameter 'Read Width B(Read_Width_B)' for BD Cell 'blk_mem_gen_0' . Valid values are - 64
• [BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors. ::xilinx.com_ip_blk_mem_gen_8.3::post_propagate Line 61
• [BD 41-241] Message from IP propagation TCL of /blk_mem_gen_0: set_property error: Value '32' is out of the range for parameter 'Read Width B(Read_Width_B)' for BD Cell 'blk_mem_gen_0' . Valid values are - 64 Customization errors found on 'blk_mem_gen_0'. Restoring to previous valid configuration.

I can't make sense from these messages because all properties are set to 64 bit.

Also the "web" port has changed its width from 4 to 8 when I set 64 bit width on data port. I guess I need to do the same in my PL code?

Please help me to solve this issue,

Thanks

[novec_16 · Accepted solution]

I love to answer my own question.

After recreating the design from scratch I was able to validate it without error messages.

This allows to conclude that Vivado could not overwrite new property settings despite I erase cache folder.

Closed.