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Visitor
Visitor
4,916 Views
Registered: ‎05-04-2014

for loop ends without iterations

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Hay! I'm using for loop with veriable counter_iteration which i'm also taking as output from the module and using reg output as register. In simulation as I leave reset state for loop get jump to its last value 65. I'm attaching code. please help

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Xilinx Employee
Xilinx Employee
6,323 Views
Registered: ‎01-03-2008
You, like many others, are thinking with a software mindset and not a hardware mindset. In hardware, loops are not dynamic they are unrolled and made static as hardware is static. So, everything in the for loop happened with no delay and the final result is shown as 65.

Loops in HDL should be used sparingly and generally for simplifying the instantiation of multiple blocks.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

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Visitor
Visitor
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Registered: ‎05-04-2014

Itsdoesn't complete iterations . Registers' value goes 65 from 0

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Visitor
Visitor
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Registered: ‎05-04-2014

Here is the Simulation

iter.JPG
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Xilinx Employee
Xilinx Employee
6,324 Views
Registered: ‎01-03-2008
You, like many others, are thinking with a software mindset and not a hardware mindset. In hardware, loops are not dynamic they are unrolled and made static as hardware is static. So, everything in the for loop happened with no delay and the final result is shown as 65.

Loops in HDL should be used sparingly and generally for simplifying the instantiation of multiple blocks.
------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com

View solution in original post

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Visitor
Visitor
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Registered: ‎05-04-2014

well that sucks !! But I got you point ! That all of the Loop iterations would be executed in one cycle .... But then we can't really say it a aloop as every Programming Language has them !!Thanx for pointing it out anyway ! I wasn't thinking about this point !! 

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Historian
Historian
4,840 Views
Registered: ‎02-25-2008

@ahmad32 wrote:

well that sucks !! But I got you point ! That all of the Loop iterations would be executed in one cycle .... But then we can't really say it a aloop as every Programming Language has them !!Thanx for pointing it out anyway ! I wasn't thinking about this point !! 


It doesn't suck. It's the way the language works, and that's because it describes hardware, not software on a sequential-exection machine.

 

Ed is correct: you're thinking like a software programmer and not a hardware engineer.

----------------------------Yes, I do this for a living.
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3,174 Views
Registered: ‎03-16-2015

u r saying that for loop will be unrolled and will be executed in parallel..if that is the case then how data dependency resolved. want say it takes into account data dependecy or not? eg Ripple carry addet using for loop will work or not?

Thanks evrybody

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